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VCS UPF 无法编译

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发表于 3 天前 | 显示全部楼层 |阅读模式

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我在vcs 2024.09 SP1 上仿真一个简单的示例,发现其无法编译,卡死在此界面,长时间无反应,求各位大佬帮忙:
注:之前的License无MVDBGEN的Feature,然后我手动加入,日志并未出现异常,但编译无法进行。

                               
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测试代码由AI生成:
执行的命令:

   

        

                
  1. vcs -full64 -sverilog design.v tb.v -upf design.upf -o simv -l compile.log
            

   

    复制代码



design.v


   

        

                
  1. module PD_DUT (
  2.   input  wire data_in,
  3.   output wire data_out
  4. );
  5.   assign data_out = data_in;
  6. endmodule


  7. module top (
  8.   input  wire clk,
  9.   input  wire top_in,
  10.   output wire top_out,
  11.   
  12.   input  wire pwr_en,
  13.   input  wire iso_en
  14. );
  15.   
  16.   PD_DUT u_dut (
  17.     .data_in  (top_in),
  18.     .data_out (top_out)
  19.   );

  20. endmodule
            

   

    复制代码
tb.v


   

        

                
  1. module tb;

  2.   reg clk;
  3.   reg top_in;
  4.   reg pwr_en;
  5.   reg iso_en;
  6.   wire top_out;

  7.   // 实例化顶层设计
  8.   top uut (
  9.     .clk(clk),
  10.     .top_in(top_in),
  11.     .top_out(top_out),
  12.     .pwr_en(pwr_en),
  13.     .iso_en(iso_en)
  14.   );

  15.   // 时钟生成
  16.   initial begin
  17.     clk = 0;
  18.     forever #5 clk = ~clk;
  19.   end

  20.   // 测试激励
  21.   initial begin
  22.     $display("T=%0t: ---- Simulation Start ----", $time);
  23.    
  24.     // 1. 初始状态:上电,不隔离
  25.     pwr_en = 1'b1; // Power on
  26.     iso_en = 1'b0; // Isolation disabled
  27.     top_in = 1'b0;
  28.     #20;
  29.     $display("T=%0t: Power is ON, Isolation is OFF. DUT should be working.", $time);
  30.     top_in = 1'b1; // 检查DUT是否工作,top_out应该跟随变为1
  31.     #20;
  32.     top_in = 1'b0;
  33.     #20;

  34.     // 2. 准备断电:先使能隔离
  35.     $display("T=%0t: ---- Starting Power Down Sequence ----", $time);
  36.     iso_en = 1'b1; // Enable isolation
  37.     #20;
  38.     $display("T=%0t: Isolation is ON. Output should be clamped to 0 now.", $time);
  39.     top_in = 1'b1; // 此时top_out应保持为0,不受top_in影响
  40.     #20;

  41.     // 3. 执行断电
  42.     pwr_en = 1'b0; // Cut the power
  43.     $display("T=%0t: Power is OFF. DUT is non-functional.", $time);
  44.     #50;

  45.     // 4. 准备上电:先给电
  46.     $display("T=%0t: ---- Starting Power Up Sequence ----", $time);
  47.     pwr_en = 1'b1; // Restore power
  48.     #20;
  49.     $display("T=%0t: Power is restored.", $time);
  50.     top_in = 1'b0;
  51.     #20;

  52.     // 5. 解除隔离,恢复正常工作
  53.     iso_en = 1'b0; // Disable isolation
  54.     $display("T=%0t: Isolation is OFF. DUT should be working again.", $time);
  55.     top_in = 1'b1; // 检查DUT是否恢复工作,top_out应该跟随变为1
  56.     #20;
  57.    
  58.     $display("T=%0t: ---- Simulation End ----", $time);
  59.     $finish;
  60.   end

  61.   // (可选) 用于在终端打印信号变化,方便调试
  62.   initial begin
  63.     $monitor("T=%0t: clk=%b, top_in=%b, pwr_en=%b, iso_en=%b, top_out=%b",
  64.              $time, clk, top_in, pwr_en, iso_en, top_out);
  65.   end

  66. endmodule

  67.         

   

    复制代码
design.upf


   

        

                
  1. # design.upf

  2. # 声明UPF版本
  3. set_upf_version "2.0"

  4. # 1. 创建一个名为 PD_A 的电源域 (Power Domain)
  5. #    -scope 指定了这个域包含的RTL实例范围
  6. create_power_domain PD_A
  7. set_scope /top/u_dut
  8. map_power_domain PD_A -elements {.}
  9. set_scope /top

  10. # 2. 定义 PD_A 域的供电网络
  11. #    - VDD 是全局主电源 (Always-On)
  12. #    - VDD_A 是 PD_A 域的虚拟电源,它将被开关控制
  13. #    - VSS 是全局地
  14. create_supply_net VDD
  15. create_supply_net VSS -domain PD_A -reuse
  16. create_supply_net VDD_A -domain PD_A

  17. # 将PD_A域的主电源连接到虚拟电源VDD_A
  18. set_domain_supply_net PD_A -primary_power_net VDD_A -primary_ground_net VSS

  19. # 3. 创建一个电源开关 (Power Switch)
  20. #    这个开关将根据 pwr_en 信号来决定是否将 VDD 连接到 VDD_A
  21. create_power_switch pwr_sw
  22.     -domain PD_A \
  23.     -input_supply_port  {in VDD} \
  24.     -output_supply_port {out VDD_A} \
  25.     -control_port {en /top/pwr_en} \
  26.     -ack_port {ack_ignored .} \
  27.     -on_state {on_ack in} \
  28.     -off_state {off_ack}

  29. # 4. 创建隔离规则 (Isolation Rule)
  30. #    当 PD_A 域断电时,其输出信号需要被隔离
  31. set_isolation iso_rule
  32.     -domain PD_A \
  33.     -isolation_power_net VDD \
  34.     -isolation_ground_net VSS \
  35.     -applies_to outputs \
  36.     -clamp_value 0 \
  37.     -isolation_signal /top/iso_en

  38. # 5. 将隔离规则与电源状态关联起来
  39. add_isolation_control iso_rule -location self -isolation_sense high

  40.         

   

    复制代码



发表于 3 天前 | 显示全部楼层


   

        

                
  1.                          Chronologic VCS (TM)
  2.        Version W-2024.09-SP1_Full64 -- Sat Aug  9 23:00:32 2025

  3.                     Copyright (c) 1991 - 2024 Synopsys, Inc.
  4.    This software and the associated documentation are proprietary to Synopsys,
  5. Inc. This software may only be used in accordance with the terms and conditions
  6. of a written license agreement with Synopsys, Inc. All other use, reproduction,
  7.    or distribution of this software is strictly prohibited.  Licensed Products
  8.      communicate with Synopsys servers for the purpose of providing software
  9.     updates, detecting software piracy and verifying that customers are using
  10.     Licensed Products in conformity with the applicable License Key for such
  11.   Licensed Products. Synopsys will use information gathered in connection with
  12.     this process to deliver software updates and pursue software pirates and
  13.                                    infringers.

  14. Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
  15.             Inclusivity and Diversity" (Refer to article 000036315 at
  16.                         https://solvnetplus.synopsys.com)

  17. Parsing included file '/tools/synopsys/vcs/W-2024.09-SP1/etc/upf/lp_msg_table.svh'.
  18. Back to file '/tools/synopsys/vcs/W-2024.09-SP1/etc/upf/upf_pnm_package.svlp'.
  19. Parsing design file 'design.v'
  20. Parsing design file 'tb.v'
  21. Top Level Modules:
  22.        tb
  23. No TimeScale specified

  24. Note-[UPF_DESIGN_TOP_DETECTION] Upf file parsing for design top
  25.   Parsing top level Upf file 'design.upf' for determining design top.


  26. Error-[TCL_COMMAND_UNKNOWN] Command not known
  27. design.upf, 5
  28.   Failure reported from Tcl interpreter. Unknown command 'set_upf_version'.


  29. Error-[TCL_COMMAND_UNKNOWN] Command not known
  30. design.upf, 11
  31.   Failure reported from Tcl interpreter. Unknown command 'map_power_domain'.


  32. Error-[TCL_OPTION_MANDATORY] Mandatory option not found
  33. design.upf, 27
  34.   Failure reported from Tcl interpreter. Required argument '-domain' was not
  35.   found.


  36. Error-[TCL_OPTION_MANDATORY] Mandatory option not found
  37. design.upf, 27
  38.   Failure reported from Tcl interpreter. Required argument
  39.   '-output_supply_port' was not found.


  40. Error-[TCL_OPTION_MANDATORY] Mandatory option not found
  41. design.upf, 27
  42.   Failure reported from Tcl interpreter. Required argument
  43.   '-input_supply_port' was not found.


  44. Error-[TCL_OPTION_MANDATORY] Mandatory option not found
  45. design.upf, 27
  46.   Failure reported from Tcl interpreter. Required argument '-control_port' was
  47.   not found.


  48. Error-[TCL_OPTION_MANDATORY] Mandatory option not found
  49. design.upf, 27
  50.   Failure reported from Tcl interpreter. Required argument '-on_state' was not
  51.   found.


  52. Error-[TCL_COMMAND_UNKNOWN] Command not known
  53. design.upf, 34
  54.   Failure reported from Tcl interpreter. Unknown command '-domain'.


  55. Error-[TCL_OPTION_MANDATORY] Mandatory option not found
  56. design.upf, 38
  57.   Failure reported from Tcl interpreter. Required argument '-domain' was not
  58.   found.


  59. Error-[TCL_COMMAND_UNKNOWN] Command not known
  60. design.upf, 44
  61.   Failure reported from Tcl interpreter. Unknown command '-domain'.


  62. Note-[MAX_ERROR_COUNT] Maximum error count reached
  63.   Current number of errors has reached the default maximum error count (10).
  64.   Please use +error+<count> to increase the limit.

  65. 10 errors
  66. CPU time: .419 seconds to compile

  67.         

   

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发表于 3 天前 | 显示全部楼层
本帖最后由 joshua2784920 于 2025-8-10 17:27 编辑



Review above post.
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 楼主| 发表于 昨天 22:50 | 显示全部楼层


   
joshua2784920 发表于 2025-8-10 14:03
Review above post.


我不太明白啥意思,可否解释一下
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