vcs编译出现错误

八阿哥

在用vcs编译测试文件时，总是出现以下错误:

Parsing design file './adder.v'
Parsing design file './add.v'
Parsing design file './adder_4.v'
Parsing design file './add_2.v'
Parsing design file './add_3.v'
Parsing design file './CLA_8.v'
Parsing design file './CLA_16.v'
Parsing design file './compress4_2.v'
Parsing design file './PartialProduct_1.v'
Parsing design file './Top_booth_1.v'
Parsing design file './test_tb1.v'

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "./test_tb1.v", 3: token is 'module'
  module test_tb1;


有没有大佬提点一下

skyze

你看看test_tb1.v代码是否语法不完整，或者贴出相关上下文代码看看，比如缺少分号，end之类的