【J M.Rabaey的书】Power Aware Design Methodologies (文字版，高清晰！)

benemale

	Power Aware Design Methodologies Pedram, Massoud, Rabaey, Jan M. 2002, 544 p., Hardcover ISBN: 978-1-4020-7152-2 Ships in 3 - 5 business days
	$150.00

About this book
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Table of contents

About this book
Power Aware Design Methodologies is on power-awareness in design. The difference between low-power design and power-awareness in design is that whereas low-power design refers to minimizing power with or without a performance constraint, power-aware design refers to maximizing some other performance metric, subject to a power budget (even while reducing power dissipation).
Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.
The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful to the circuit and system designers, tool developers, and academic researchers and students.
Power Aware Design Methodologies is written for the design professional and can be used as a textbook for an advanced course on power-aware design methodologies.

Written for:
Circuit and system designers, tool developers, academic researchers, students

[ 本帖最后由 benemale 于 2008-3-6 22:40 编辑 ]

benemale

Chapter 1 Introduction
Massoud Pedram, Jan Rabaey
University of Southern California; University of California, Berkeley

Chapter 2 CMOS Device Technology Trends for Power-Constrained Applications
David J. Frank
IBM T. J. Watson Research Center

Chapter 3 Low Power Memory Design
Yukihito Oowaki and Tohru Tanzawa
SoC R&D Center, Toshiba Corp.

Chapter 4 Low-Power Digital Circuit Design
Tadahiro Kuroda
Keio University

Chapter 5 Low Voltage Analog Design
K. Uyttenhove and M. Steyaert
Katholieke Universiteit Leuven, ESAT-MICAS

Chapter 6 Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip
Chulwoo Kim and Sung-Mo (Steve) Kang
IBM, Microelectronics Division, Austin, TX; University of California, Santa Curz, CA

Chapter 7 Power Optimization by Datapath Width Adjustment
Hiroto Yasuura and Hiroyuki Tomiyama
System LSI Research Center, Kyushu University; Institute of System and Information
Technologies /Kyushu

Chapter 8 Energy-Efficient Design of High-Speed Links
Gu-Yeon Wei, Mark Horowitz, Jaeka Kim
Harvard University; Stanford University

Chapter 9 System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing
Diana Marculescu and Radu Marculescu
Carnegie Mellon University

Chapter 10 Tools and Techniques for Integrated Hardware-softwareEnergy Optimizations
N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, and M. J. Irwin
Microsystems Design Lab. Pennsylvania State University, University Park, PA 16802

Chapter 11 Power-aware Communication Systems
Mani Srivastava
University of California, Los Angeles

Chapter 12 Power-Aware Wireless Microsensor Networks
Rex Min, Seong-Hwan Cho, Manish Bhardwaj, Eugene Shih, Alice Wang,Anantha Chandrakasan
Massachusetts Institute of Technology

Chapter 13 Circuit and System Level Power Management
Farzan Fallah and Massoud Pedram
Fujitsu Labs. of America, Inc.;  University of Southern California

Chapter 14 Tools and Methodologies for Power Sensitive Design
Jerry Frenkil
Sequence Design, Inc.

Chapter 15 Reconfigurable Processors — The Road to Flexible Power-Aware Computing
J. Rabaey, A. Abnous, H. Zhang, M. Wan, V. George, V. Prabhu
University of California at Berkeley

Chapter 16 Energy-Efficient System-Level Design
Luca Benini and Giovanni De Micheli
University di Bologna; Stanford University

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