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##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: DFF.lvs.report
LAYOUT NAME: /home/IC/Desktop/B/lvstext/DFF.sp ('DFF')
SOURCE NAME: /home/IC/Desktop/B/lvstext/DFF.src.net ('DFF')
RULE FILE: /home/IC/Desktop/B/lvstext/_SmicSP12R_cal018_epm_sali_p2mtx_18335155.lvs_
CREATION TIME: Sat Jul 5 21:08:10 2025
CURRENT DIRECTORY: /home/IC/Desktop/B/lvstext
USER NAME: IC
CALIBRE VERSION: v2019.3_15.11 Tue Jul 2 12:24:58 PDT 2019
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets.
Error: Different numbers of instances.
Error: Connectivity errors.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT DFF DFF
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "VDD"
LVS GROUND NAME "VSS"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES NONE
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
// LVS SPICE EXCLUDE CELL SOURCE
// LVS SPICE EXCLUDE CELL LAYOUT
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 65536
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// LVS IGNORE DEVICE PIN
// LVS PREFER NETS FILTER SOURCE
// LVS PREFER NETS FILTER LAYOUT
LVS PREFER PORT NETS NO
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE rndif_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rndif_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rpdif_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rpdif_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnpo_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnpo_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnpo_3t_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnpo_3t_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rppo_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rppo_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rppo_3t_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rppo_3t_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnwaa_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnwaa_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnwsti_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnwsti_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rndifsab_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rndifsab_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rpdifsab_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rpdifsab_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnposab_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnposab_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnposab_3t_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rnposab_3t_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rpposab_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rpposab_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rpposab_3t_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rpposab_3t_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rhrpo_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rhrpo_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rhrpo_3t_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rhrpo_3t_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCE rtimsabe2r_ckt SERIES PLUS MINUS [ TOLERANCE W 0 L 0 ]
LVS REDUCE rtimsabe2r_ckt PARALLEL [ TOLERANCE W 0 L 0 ]
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY mn(n18e2r) l l 5
TRACE PROPERTY mn(n18e2r) w w 5
TRACE PROPERTY mn(nz18e2r) l l 5
TRACE PROPERTY mn(nz18e2r) w w 5
TRACE PROPERTY mp(p18e2r) l l 5
TRACE PROPERTY mp(p18e2r) w w 5
TRACE PROPERTY mn(n33e2r) l l 5
TRACE PROPERTY mn(n33e2r) w w 5
TRACE PROPERTY mp(p33e2r) l l 5
TRACE PROPERTY mp(p33e2r) w w 5
TRACE PROPERTY mn(n50e2r) l l 5
TRACE PROPERTY mn(n50e2r) w w 5
TRACE PROPERTY mp(p50e2r) l l 5
TRACE PROPERTY mp(p50e2r) w w 5
TRACE PROPERTY mn(nz50e2r) l l 5
TRACE PROPERTY mn(nz50e2r) w w 5
TRACE PROPERTY mn(n155e2r) l l 5
TRACE PROPERTY mn(n155e2r) w w 5
TRACE PROPERTY mn(nz155e2r) l l 5
TRACE PROPERTY mn(nz155e2r) w w 5
TRACE PROPERTY mp(p155e2r) l l 5
TRACE PROPERTY mp(p155e2r) w w 5
TRACE PROPERTY mn(n18d) l l 5
TRACE PROPERTY mn(n18d) w w 5
TRACE PROPERTY mn(n18h) l l 5
TRACE PROPERTY mn(n18h) w w 5
TRACE PROPERTY mn(nsg) l l 5
TRACE PROPERTY mn(nsg) w w 5
TRACE PROPERTY mn(ncg) l l 5
TRACE PROPERTY mn(ncg) w w 5
TRACE PROPERTY pvar18e2r_ckt wr wr 5
TRACE PROPERTY pvar18e2r_ckt lr lr 5
TRACE PROPERTY pvar18e2r_ckt nf nf 0
TRACE PROPERTY q(pnp18a4e2r) a a 5
TRACE PROPERTY q(pnp18a25e2r) a a 5
TRACE PROPERTY q(pnp18a100e2r) a a 5
TRACE PROPERTY q(pnp33a4e2r) a a 5
TRACE PROPERTY q(pnp33a25e2r) a a 5
TRACE PROPERTY q(pnp33a100e2r) a a 5
TRACE PROPERTY d(pdio18e2r) a a 5
TRACE PROPERTY d(pdio33e2r) a a 5
TRACE PROPERTY d(pdio50e2r) a a 5
TRACE PROPERTY d(pdio155e2r) a a 5
TRACE PROPERTY d(ndio18e2r) a a 5
TRACE PROPERTY d(ndio33e2r) a a 5
TRACE PROPERTY d(ndio50e2r) a a 5
TRACE PROPERTY d(ndio155e2r) a a 5
TRACE PROPERTY d(nzdio50e2r) a a 5
TRACE PROPERTY d(nzdio155e2r) a a 5
TRACE PROPERTY d(nwdioe2r) a a 5
TRACE PROPERTY d(dnwdioe2r) a a 5
TRACE PROPERTY c(cgttow) c c 5
TRACE PROPERTY pipe2r_ckt c c 5
TRACE PROPERTY mime2r_ckt lr lr 5
TRACE PROPERTY mime2r_ckt wr wr 5
TRACE PROPERTY r(rpgt) r r 5
TRACE PROPERTY r(rngtsab) r r 5
TRACE PROPERTY r(rpgtsab) r r 5
TRACE PROPERTY r(rncgsab) r r 5
TRACE PROPERTY rndif_ckt w w 5
TRACE PROPERTY rndif_ckt l l 5
TRACE PROPERTY rpdif_ckt w w 5
TRACE PROPERTY rpdif_ckt l l 5
TRACE PROPERTY rnpo_ckt w w 5
TRACE PROPERTY rnpo_ckt l l 5
TRACE PROPERTY rnpo_3t_ckt w w 5
TRACE PROPERTY rnpo_3t_ckt l l 5
TRACE PROPERTY rppo_ckt w w 5
TRACE PROPERTY rppo_ckt l l 5
TRACE PROPERTY rppo_3t_ckt w w 5
TRACE PROPERTY rppo_3t_ckt l l 5
TRACE PROPERTY rnwaa_ckt w w 5
TRACE PROPERTY rnwaa_ckt l l 5
TRACE PROPERTY rnwsti_ckt w w 5
TRACE PROPERTY rnwsti_ckt l l 5
TRACE PROPERTY rndifsab_ckt w w 5
TRACE PROPERTY rndifsab_ckt l l 5
TRACE PROPERTY rpdifsab_ckt w w 5
TRACE PROPERTY rpdifsab_ckt l l 5
TRACE PROPERTY rnposab_ckt w w 5
TRACE PROPERTY rnposab_ckt l l 5
TRACE PROPERTY rnposab_3t_ckt w w 5
TRACE PROPERTY rnposab_3t_ckt l l 5
TRACE PROPERTY rpposab_ckt w w 5
TRACE PROPERTY rpposab_ckt l l 5
TRACE PROPERTY rpposab_3t_ckt w w 5
TRACE PROPERTY rpposab_3t_ckt l l 5
TRACE PROPERTY rhrpo_ckt w w 5
TRACE PROPERTY rhrpo_ckt l l 5
TRACE PROPERTY rhrpo_3t_ckt w w 5
TRACE PROPERTY rhrpo_3t_ckt l l 5
TRACE PROPERTY rtimsabe2r_ckt w w 5
TRACE PROPERTY rtimsabe2r_ckt l l 5
TRACE PROPERTY r(rm1) r r 5
TRACE PROPERTY r(rm2) r r 5
TRACE PROPERTY r(rm3) r r 5
TRACE PROPERTY r(rm4) r r 5
TRACE PROPERTY r(rm5) r r 5
TRACE PROPERTY r(rm6) r r 5
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.
LAYOUT CELL NAME: DFF
SOURCE CELL NAME: DFF
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 8
Nets: 17 19 *
Instances: 15 15 MN (4 pins)
15 15 MP (4 pins)
------ ------
Total Inst: 30 30
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 8
Nets: 13 15 *
Instances: 3 0 * MN (4 pins)
2 0 * _invb (6 pins)
3 3 _invv (4 pins)
2 4 * _nor2v (5 pins)
2 0 * _sup2v (4 pins)
1 2 * _tgmb (7 pins)
------ ------
Total Inst: 13 9
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net SD SD
--- 14 Connections On This Net --- --- 3 Connections On This Net ---
-------------------------- --------------------------
(_sup2v) ut1 ** missing connection **
X7/M3(8.760,5.535):s
(_sup2v):in2 ** missing connection **
X7/M3(8.760,5.535):g
(_sup2v)ut1 ** missing connection **
X10/M3(31.140,5.535):s
(_sup2v):in1 ** missing connection **
X10/M2(29.600,5.535):g
(_nor2v):in2 ** missing connection **
X8/M1(16.220,0.950):g
X8/M3(16.220,5.535):g
(_invb):sup2 ** missing connection **
X6/X1/M0(26.520,0.950):d
(_invb):sup1 ** missing connection **
X5/X0/M0(19.060,5.535):s
(_invb):sup2 ** missing connection **
X5/X1/M0(19.060,0.950):s
(_invb):sup1 ** missing connection **
X6/X0/M0(26.520,5.535):d
X10/M1(31.140,0.950):d ** missing connection **
X7/M1(8.760,0.950):d ** missing connection **
X7/M1(8.760,0.950):g ** missing connection **
X7/M0(7.220,0.950):s ** missing connection **
** missing connection ** (_nor2v):in1
XI12/MNM0:g
XI12/MPM1:g
** missing connection ** (_nor2v):in2
XI11/MNM1:g
XI11/MPM0:g
--------------------------------------------------------------------------------------------------------------
2 ** missing net ** net28
--------------------------------------------------------------------------------------------------------------
3 ** missing net ** net55
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
4 X7/M0(7.220,0.950) MN(N18E2R) ** missing instance **
--------------------------------------------------------------------------------------------------------------
5 X7/M1(8.760,0.950) MN(N18E2R) ** missing instance **
--------------------------------------------------------------------------------------------------------------
6 X10/M1(31.140,0.950) MN(N18E2R) ** missing instance **
--------------------------------------------------------------------------------------------------------------
7 (_invb) ** missing injected instance **
Devices:
X6/X0/M0(26.520,5.535) MP(P18E2R)
X5/X1/M0(19.060,0.950) MN(N18E2R)
--------------------------------------------------------------------------------------------------------------
8 (_invb) ** missing injected instance **
Devices:
X5/X0/M0(19.060,5.535) MP(P18E2R)
X6/X1/M0(26.520,0.950) MN(N18E2R)
--------------------------------------------------------------------------------------------------------------
9 (_sup2v) ** missing injected instance **
Devices:
X10/M2(29.600,5.535) MP(P18E2R)
X10/M3(31.140,5.535) MP(P18E2R)
--------------------------------------------------------------------------------------------------------------
10 (_sup2v) ** missing injected instance **
Devices:
X7/M2(7.220,5.535) MP(P18E2R)
X7/M3(8.760,5.535) MP(P18E2R)
--------------------------------------------------------------------------------------------------------------
11 ** missing injected instance ** (_tgmb)
Devices:
XI3/MPM0 MP(P18E2R)
XI2/MPM0 MP(P18E2R)
XI2/MNM0 MN(N18E2R)
XI3/MNM0 MN(N18E2R)
--------------------------------------------------------------------------------------------------------------
12 ** missing injected instance ** (_nor2v)
Devices:
XI11/MPM1 MP(P18E2R)
XI11/MPM0 MP(P18E2R)
XI11/MNM0 MN(N18E2R)
XI11/MNM1 MN(N18E2R)
--------------------------------------------------------------------------------------------------------------
13 ** missing injected instance ** (_nor2v)
Devices:
XI12/MPM1 MP(P18E2R)
XI12/MPM0 MP(P18E2R)
XI12/MNM0 MN(N18E2R)
XI12/MNM1 MN(N18E2R)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 8 8 0 0
Nets: 13 13 0 2
Instances: 0 0 3 0 MN(N18E2R)
0 0 2 0 _invb
3 3 0 0 _invv
2 2 0 2 _nor2v
0 0 2 0 _sup2v
1 1 0 1 _tgmb
------- ------- --------- ---------
Total Inst: 6 6 7 3
o Statistics:
2 layout mos transistors were reduced to 1.
1 mos transistor was deleted by parallel reduction.
o Initial Correspondence Points:
Ports: VDD VSS D SD RD CLK Q QB
**************************************************************************************************************
DETAILED INSTANCE CONNECTIONS
LAYOUT NAME SOURCE NAME
**************************************************************************************************************
(This section contains detailed information about connections of
matched instances that are involved in net discrepancies).
--------------------------------------------------------------------------------------------------------------
(_nor2v) (_nor2v)
in1: RD in1: RD
out: 7 out: net23
sup1: VDD sup1: VDD
sup2: VSS sup2: VSS
in2: SD ** SD **
** missing net ** in2: net55
Devices:
X8/M2(14.680,5.535) MP(P18E2R) XI13/MPM1 MP(P18E2R)
X8/M3(16.220,5.535) MP(P18E2R) XI13/MPM0 MP(P18E2R)
X8/M0(14.680,0.950) MN(N18E2R) XI13/MNM0 MN(N18E2R)
X8/M1(16.220,0.950) MN(N18E2R) XI13/MNM1 MN(N18E2R)
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec
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