后仿真中的负延迟

dzlyl

其实，不是所有负延时都是不可接受的。负延时的产生是由于同一输出驱动很多路径时，负载差别大引起的（当然还有其他原因），可以先仿真，依结果决定如何修改设计。

kevinliu

[这个贴子最后由kevinliu在 2005/05/31 00:21am 第 2 次编辑]

NCVerilog will ignore those negative timing annotations (zero), but for negative timing check, you need to define NEG_TCHK and use merged setuphold (recrem) to enable it (SDF 3.0), otherwise, it'll be zeroed (too pessimistic).
there is one paper on Solvit about negative timing. basically, it's caused by delay calculation (trippoint) and transition.

jingli888ca

建议检查一下时钟飘逸

niko

但是有的库就是包含了负值.这怎么理解呢?(hold time value)

huangzhang

谢谢各个

vlog

学习一下，不错

brianliu

negative propagation delay is perfectly fine, most likely it's caused by an input with slow transition , however, the output transition delay is small. since propagation delay is calculated from 50% input to 50% output, that's how the negative propagation delay comes from.
ncvlog shall be able to handle it properly by zeroing out all the negative delay during sdf annotation - which is more pessimistic.

liuyangqwin2

出现负延迟   是好还是坏啊？

liuyangqwin2

回复 17# brianliu


    ncverilog中结果更悲观？就是说悲观的结果，波形都对了，那设计就没问题咯？