上海KT人才招聘 ASIC设计 相关人才

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上海KT人公司是中国最大最专业的IC电子人才咨询公司之一，多年来专注于IC与电子行业中高级人才服务，客户主要为欧美著名半导体公司（如TI、ADI、LSI、Cisco、Conexant等）和美资集成电路设计新公司共20多家，主要寻找IC设计、芯片制造、IC市场与销售、IC应用（硬件与底层嵌入式驱动软件开发）等人才。
现受某美资公司委托招聘IC设计相关人才：
一、ASIC Design Engineer

Participate in the design and verification of complex, high performance and high integration ASICs used in Cisco Switch and Router.
Responsibilities include:
Detail design spec and test plan development.
RTL logic design, synthesis and timing closure.
Module level and full chip verification, formal verification and equivalence checking.
Assist in prototype bring up and verification in the lab.

Education
Typically requires BSEE/CS combined with 2-4+ yrs related experience, or MSEE/CS combined with 1-2 years of related experience.
Skills Required
Knowledge of Verilog or VHDL, scripting and programming languages (Perl, TCL, C and C++) and HDL design tools.
Understanding in ASIC methodologies and flows.
Strong background in logic design.
Excellent written and verbal communications, team and people skills.
Self motivated and willing to learn on the job.



二、STA  Engineer
Job Responsibilities:
==============
Duties will include working within a Product Development Team to work on leading edge ASIC
solutions in full custom and SoC environments. Design IC devices in conformance with both
LSI and customer requirements and sound design principles; Place and route(layout)
of integrated circuits to meet design requirements; Prepare project evaluations in conformance
with company policies/procedures; Provide CAD assistance to customer engineers and new staff
as required and/or requested; Keep up-to-date with all technical memos; Attend peer reviews
and provide feedback to ensure success of peer designs. Ideal candidate will have
experience/exposure to ASIC and full custom high-speed digital flows from design handoff
through manufacturing, and with strong timing analysis capabilities. Excellent communication
skills are needed, as the existing team spans multiple locations.

Qualifications :
===========
Functional/Industry Knowledge
Required:
- Minimum of 4-6 years experience in Physical Design in a product development environment
- Proven physical design experience
- Expertise in circuit design, place and routing, signal integrity, power analysis, CTS design, DFT,
design rule and connectivity verification
- Strong timing analysis capabilities
- Good analytical and debugging skills
- Extremely disciplined in conducting checks and audits
- Must be technically adept, a strong team player, ability to manage multiple priorities
- Strong written and verbal communication skills
- Ability to interact intelligently and politely with customers
Desired:
- Familiarity with analog physical design, manufacturing and IC packaging
- Past experience in a lead position giving guidance to other engineers

Education/Certifications :
===================
Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline




三、DFT Engineer
Job Description
Hardware Engineers who participate in the design of various networking products.  Implement Design for Test strategy from the component level, ASIC level, and all the way to system level.  Be responsible for component and system level DFT sign off.  Participate in driving new DFT methodology and solutions to improve quality of the hardware reliability and in system test and debug capability.
Daily responsibilities include:
-Implement basic DFT schemes in terms of BIST, scan, boundary scan on ASICs.
-Generate tests which achieve highest possible ASIC component test coverage with lowest overhead.
-Verify all DFT logics and test patterns with simulation and static timing analysis tool.
-Implement and verify advanced DFT logics like logic BIST, high speed interface test logic etc.
-Participate in new DFT methodology discussion and solution generation.
-Architect ASIC DFT designs into system DFT designs
Skills Required
-Good knowledge in Design for Test in general.  Understand the concepts of BIST, SCAN, Boundary Scan, ATPG.
-Experience in ASIC DFT design, Testability, and Reliability issues.
-Hands on familiarity with various ASIC DFT analysis, synthesis, and verification tools.
-Familiar with fault coverage and board/system testability analysis and enhancement technique, DFT economics analysis/justification technique.
-Hands on knowledge of simulation and verification debug tools.
-Good knowledge of test engineering in terms of ASIC test program generation, understanding of testers and associated hardware is a plus.
-Working knowledge using Verilog HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
-Excellent written and verbal communications, team and people skills.
Educational Background
DFT Engineer: Typically requires MSEE/CS combined with 3+ years experience, or BSEE/CS combined with 5+ yrs experience.
Senior Engineer: Typically requires MSEE/CS combined with 7+ years experience, or BSEE/CS combined with 8+ yrs experience.



四、Physical Design Engineers

Job Responsibilities:
- In Charge of Digital Back-end Physical Design & automation;
- Main responsibilities include circuit synthesis, physical synthesis, static timing analysis, chip floorplanning, auto place and route, capacitance and resistance extraction, design rule checking and delay back-annotation;
- Responsible for clock tree synthesis, scan chain generation, critical path timing analysis and power analysis.
- DRC/LVS command file writing and maintainence

Requirements:
- BS or above with major in EE or Computer Science related field;
- Familiar with floorplan, placement/routing, CTS, and LVS/DRC design flow and be capable of running projects independently;
- Experience with timing driven design flow preferred;
- Experience with DSM IC design or process, and familiar with device modeling, crosstalk, IR drop analysis, preferred.

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******
Dolphin   Shen
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