verilogA

cyplay

verilogA只能用于spectre仿真吗   在cadencevirtuoso里verilog模块好像必须AMS仿真  可是verilogA不支持AMS仿真  那怎么兼容呢  必须统一语言了吗   
新手求教，谢谢

zt_ic222

verilogA是用来建模用的，不能综合成实际电路，verilog是数字设计语言，可以综合出实际电路的

cyplay

zt_ic222 发表于 2025-3-5 19:24
verilogA是用来建模用的，不能综合成实际电路，verilog是数字设计语言，可以综合出实际电路的 ...

我这边现在有一个阈值开关器件是用veriloga写的  不需要综合成电路；但是仿真的时候需要把这个器件带入进去一起仿，我想找找有没有可以兼容spectre仿真的verilog

zt_ic222

cyplay 发表于 2025-3-5 20:06
我这边现在有一个阈值开关器件是用veriloga写的  不需要综合成电路；但是仿真的时候需要把这个器件带入进 ...

ams仿真，建config把verilog的function加进去即可，而veriloga直接建symbol就跟普通模拟仿真一样就行，俩个名字虽然相似，但是完全不同的东西，你的开关是veriloga，你就spectre直接仿啊

cyplay

                               
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verilogA好像不能用AMS仿真  我创建cofig然后再混合仿真  他直接给了err

cyplay

zt_ic222 发表于 2025-3-5 20:11
ams仿真，建config把verilog的function加进去即可，而veriloga直接建symbol就跟普通模拟仿真一样就行，俩 ...

是的  我是按照你说的做的  创建config  然后verilog的模块加function  电路部分用schematic   veriloga部分用的symbol   然后在ADE Explorer里进行AMS仿真  但是最后跑不出来  他会报错error

报错日志：

For more details, consult the job log file:
/home/chengy/work/logs_chengy/logs0/Job1.log
Deleted view binding for instance 'I8' in cellview (SNN_SPK_TEST test_count schematic).
WARNING (ADE-5723): Config view of SNN_SPK_TEST of test_count has changed, therefore reopening the modified config view.
ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.
ERROR (EXPLORER-5031): While simulating run ExplorerRun.0, point 1, test SNN_SPK_TEST:test_count:1, received error:
Simulation Error:
------------------------------
Simulator failed to complete the simulation.
The simulator process returned a non-zero exit code, indicating failure.
The simulator could have crashed or intentionally returned to indicate an error.
Check the simulator log file for more information.  Common causes:
1. Simulator may have crashed during exit even after reporting success in log file.
2. Abrupt automatic simulator termination (e.g., SIGKILL) because the simulator process has
   exceeded resource limits, which can be specified in the distribution system or
   by the kernel itself (e.g., the Linux OOMKiller).
3. Manual termination of the simulator process.
./runSimulation can be manually run in this directory to check the issue.

For details open log: /home/chengy/simulation/SNN_SPK_TEST/test_count/maestro/results/maestro/ExplorerRun.0/1/SNN_SPK_TEST:test_count:1/psf/irun.log for the point: (3 1)
------------------------------

For more details, consult the job log file:
/home/chengy/work/logs_chengy/logs0/Job1.log

zt_ic222

ams不能跑veriloga，

你要么全用verilog，跑ams，要么全用veriloga，跑spectre

zt_ic222

你把你的veriloga，用verilog写一遍，不能综合没问题，能出预设结果就行

cyplay

zt_ic222 发表于 2025-3-6 10:34
你把你的veriloga，用verilog写一遍，不能综合没问题，能出预设结果就行

好的好的  谢谢你