Extension of a Verification Framework for RISC-V Instruction Set Implementations

huikong2013

https://dl.acm.org/doi/10.1007/978-3-031-46077-7_15
AbstractCompliance testing is mandatory when implementing the hardware architecture of a specific RISC-V instruction set. An official compliance test suite with handwritten test cases can be helpful for this verification task. However, a high-quality test suite requires significant manual effort and cannot easily adapt to specific processor hardware architecture organization implementation aspects such as single-cycle, multi-cycle, or pipeline (with a different number of pipeline stages) configurations. This issue can be resolved by using an automatic test generation framework. However, these frameworks require the execution of a golden reference model for functional verification, which increases the verification time and introduces additional error possibilities. This paper extends the PATARA framework, based on the REVERSI approach, to generate randomized, self-testing test cases for any RISC-V hardware implementation. The REVERSI method takes profit of the instruction set to reverse the functionality of one instruction with other ones, verifying the functionality within the same test program and without requiring a golden reference model (e.g., simulator). The PATARA framework is extended to generate tests covering all possible hardware architecture implementation hazards and cache misses by taking into account different processor architecture parameters. In order to validate the methodology, a case study is used to verify a 6 pipeline-stages RV32IM hardware architecture implementation, reaching up to 100 % condition coverage with the REVERSI self-testing approach against 78.94% coverage achieved by the official handwritten compliance test framework.