Verdi undefined module :VCS+Verdi仿真Xilinx IP ,Verdi波形中找不到Xilinx IP

jumpyoung · 发表于 2024-11-19 18:50:31

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本帖最后由 jumpyoung 于 2024-11-19 19:47 编辑

按照网上的步骤编译VCS仿真库，没有报错。compile、elaborate、sim都没有error和warning.但是用Verdi打开设计时Xilinx的 IP 都是 undefined mudule.谁知道这个怎么解决吗？
报错截图

Makefile 内容

f_v = ./Temp/filelist_v.f
f_sv = ./Temp/filelist_sv.f
verdi_dir = /usr/Synopsys/verdi/R-2020.12-SP1/share/PLI/VCS/linux64
glbl_home = /usr/Xilinx/Vivado2022.1/Vivado/2022.1/data/verilog/src
SIM_PATH =$(shell pwd)
SRC_PATH =$(SIM_PATH)/Source
macro_sim =$(SIM_PATH)/Macro
Bench_Home =$(SIM_PATH)/Testbench
Bench_File =$(notdir $(wildcard $(Bench_Home)/*.v $(Bench_Home)/*.sv))
Bench_Name =$(basename $(Bench_File))
all: clean filelist compile elaborate simulate verdi
compile:
vlogan \
-full64 \
-work Xilinx_Lib \
$(SIM_PATH)/Temp/glbl.v \
-f $(f_sv) \
-f $(f_v) \
+v2k \
-override_timescale=1ps/1ps \
+warn=all \
+incdir+$(macro_sim) \
-l $(SIM_PATH)/Temp/VCS/Compile.log \
-sverilog \
+define+SIMULATION_EN
elaborate:
vcs \
-full64 \
-Mdir=$(SIM_PATH)/Temp/VCS/work \
-sverilog \
-override_timescale=1ps/1ps \
-lca \
+lint=TFIPC-L \
+lint=PCWM \
-debug_acc+all \
-P $(verdi_dir)/novas.tab $(verdi_dir)/pli.a \
-cm line+cond+fsm+tgl+branch \
-cm_dir $(SIM_PATH)/Temp/VCS/ \
-cm_log Coverage.log \
-l $(SIM_PATH)/Temp/VCS/Elaborate.log \
Xilinx_Lib.glbl \
Xilinx_Lib.$(Bench_Name) \
-o $(SIM_PATH)/Temp/VCS/simv
simulate:
$(SIM_PATH)/Temp/VCS/simv -l $(SIM_PATH)/Temp/VCS/Simulate.log +notimingcheck +nospecify -k $(SIM_PATH)/Temp/VCS/ucli.key
verdi:
verdi -sv -f $(f_sv) -f $(f_v) -top $(Bench_Name) -ssf $(SIM_PATH)/WaveFile/*.fsdb
clean:
@rm -rf csrc DVEfiles simv simv.daidir ucli.key VCS* AN.DB 64 verdiLog
@rm -rf novas.*
@rm -rf *.log *.vpd *.ddc *.svf *.SDF *Synth *Netlist* work vsim* transcript
@rm -rf ./Temp
@mkdir ./Temp
@mkdir ./Temp/VCS
@mkdir ./Temp/VCS/work
filelist:
@cp $(glbl_home)/glbl.v $(SIM_PATH)/Temp
[url=home.php?mod=space&uid=205858]@find[/url] $(SRC_PATH) -path "$(SRC_PATH)/Ipcore" -prune -o -type f -name "*.v" >Temp/filelist_v.f
[url=home.php?mod=space&uid=205858]@find[/url] $(SIM_PATH)/Macro/ -name "*.h" >Temp/filelist_h.f
@find $(SIM_PATH)/Testbench/ -name "*.v" >>Temp/filelist_v.f
@find $(SIM_PATH)/Ipcore/ -name "*netlist.v" >>Temp/filelist_v.f
@find $(SIM_PATH)/Model/ -name "*.v" >>Temp/filelist_v.f
@find $(SRC_PATH) -path "$(SRC_PATH)/Ipcore" -prune -o -type f -name "*.sv" >Temp/filelist_sv.f
@find $(SIM_PATH)/Testbench/ -name "*.sv" >>Temp/filelist_sv.f
@find $(SIM_PATH)/Ipcore/ -name "*netlist.sv" >>Temp/filelist_sv.f
@find $(SIM_PATH)/Model/ -name "*.sv" >>Temp/filelist_sv.f
help:
[url=home.php?mod=space&uid=17569]@echo[/url] "******Welcome******"
@echo " COMMAND LIST: "
@echo "1--- make clean "
@echo "2--- make filelist "
@echo "3--- make compile "
@echo "4--- make elaborate "
@echo "5--- make simulate "
@echo "6--- make verdi "
@echo "7--- one-click simulation, please use the command --- make all"

复制代码

synopsys_sim.setup

Xilinx_Lib : ./Temp/VCS/work
OTHERS=/usr/Xilinx/VivadoLib/synopsys_sim.setup

复制代码

Verdi undefined module :VCS+Verdi仿真Xilinx IP ,Verdi波形中找不到Xilinx IP

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