smic18ee工艺库mime2r_ckt电容和mime2r电容lvs问题

陈福刚 · 发表于 2024-11-8 22:55:06

就是我使用smic18ee工艺库的mime2r的电容，版图中也是显示mime2r,可是当我跑LVS的时候，显示原理图和版图中的电容不匹配。

当我把原理图的电容换成mime2r时，就显示下面的错误

acrofoxAgain · 发表于 2024-11-8 22:55:07

陈福刚发表于 2024-11-9 12:37
但是我看LVS里面有两个文件，其中一个就是empty_subckt.sp_cal，且里面也有关于mime2r_ckt的描述。请问问 ...

就这个文件，在source网表里include。自己Export CDL的话，里面有这一项，填上路径。GUI自动导出的话，在Calibre/Setup中可以指定导出原理图网表时添加include文件。

fengrlove · 发表于 2024-11-9 08:36:15

lvs rule file开头的options改了么

acrofoxAgain · 发表于 2024-11-9 09:50:28

下图，cdl网表少include一个文件，文件应该与LVS规则文件一起，里面定义的PDK器件的空subckt

陈福刚 · 发表于 2024-11-9 12:37:08

acrofoxAgain 发表于 2024-11-9 09:50
下图，cdl网表少include一个文件，文件应该与LVS规则文件一起，里面定义的PDK器件的空subckt ...

但是我看LVS里面有两个文件，其中一个就是empty_subckt.sp_cal，且里面也有关于mime2r_ckt的描述。请问问题在哪

陈福刚 · 发表于 2024-11-9 12:46:50

fengrlove 发表于 2024-11-9 08:36
lvs rule file开头的options改了么

///////////////////////////////////////////////////////////////////////////////////
//                            Environment Setting                            //
///////////////////////////////////////////////////////////////////////////////////

//---------------------------------------------------------------------------------

//*OPTION 1: Define TOP Metal. The value can be 6, 5, 4, 3

#DEFINE TOPMETAL 6

//----------------------------------------------------------------------------------

//*OPTION 2: Define ERC Check or Not. The value can be TRUE or FALSE(Upper Case).

#DEFINE ERCCHECK TRUE

//----------------------------------------------------------------------------------

//*OPTION 3: Define Property of resistor. The value can be WL or R.
//* WL(Upper Case): Using W & L as the property of Resistor.
//* R(Upper Case) : Using R as the property of Resistor.

#DEFINE RES_PROPERTY WL

//----------------------------------------------------------------------------------

//*OPTION 4: Define Property of MIM. The value can be WL or C.
//* WL(Upper Case): Using WR & LR as the property of MIM.
//* C(Upper Case) : Using C as the property of MIM.

#DEFINE MIM_PROPERTY WL

//----------------------------------------------------------------------------------

//*OPTION 5: Define Property of PIP. The value can be WL or C.
//* WL(Upper Case): Using WR & LR as the property of PIP.
//* C(Upper Case) : Using C as the property of PIP.

#DEFINE PIP_PROPERTY WL

//----------------------------------------------------------------------------------

//*OPTION 6: Define interface resistance or not. The value can be TRUE or FALSE.
//*TRUE(Upper Case)  : Total resistance R = Rsh*L/(W-2*DW)+2*Rint
//*FALSE(Upper Case) : Total resistance R = Rsh*L/(W-2*DW)

#DEFINE ADD_RINT TRUE

//----------------------------------------------------------------------------------

SOURCE PATH "test_res_ckt.cdl"
SOURCE PRIMARY "test_res_ckt"
SOURCE SYSTEM SPICE

LAYOUT PATH "test_res_ckt.gds"
LAYOUT PRIMARY "test_res_ckt
LAYOUT SYSTEM GDSII

LVS REPORT "lvs.rep"
LVS REPORT OPTION A B C D S

UNIT CAPACITANCE FF
UNIT RESISTANCE OHM
UNIT LENGTH U

ERC MAXIMUM RESULTS 100
ERC RESULTS DATABASE erc.db
ERC SUMMARY REPORT erc.sum
MASK SVDB DIRECTORY "svdb" QUERY
FLAG SKEW YES
FLAG OFFGRID YES
LVS SPICE PREFER PINS       YES
LVS ISOLATE SHORTS          YES
LVS RECOGNIZE GATES          NONE
LVS ABORT ON SUPPLY ERROR    NO
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS IGNORE PORTS             NO
LVS CHECK PORT NAMES          YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE PARALLEL MOS       YES
LVS REDUCE PARALLEL DIODES    YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE PARALLEL RESISTORS  YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE SPLIT GATES       YES
LVS FILTER UNUSED OPTION AB RC RE RG
LVS PROPERTY RESOLUTION MAXIMUM 65536
LAYOUT TOP LAYER M1 V1 M2 V2 M3 V3 M4 V4 M5 V5 M6
VIRTUAL CONNECT COLON YES

LVS GROUND NAME "VSS" "SAVSS?" "?GND?" "?VSS?" "?vss?" "?gnd?"
LVS POWER NAME  "VDD" "SAVDD?" "?VDD?" "?VCC?" "?vcc?" "?vdd?"

//////////////////////////////////////////////
// Layer Mapping                         //