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发表于 2024-10-30 09:49:44
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module test(mask,data_i,data_o);
input [15:0] mask;
input [127:0] data_i;
output[31:0] data_o;
wire[31:0] data_tmp;
integer bit_shift;
for (bit_shift = 0;bit_shift < 16;bit_shift = bit_shift + i) begin
if(mask[bit_shift]) begin
data_tmp = {data_i[ (bit_shift+1)*8-1 : bit_shift*8 ], data_tmp[31:8]};
end
end
assign data_o = data_tmp;
endmodule
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