做LVS时 net和instances

huangbobo · 发表于 2024-10-29 09:21:31

本帖最后由 huangbobo 于 2024-10-31 00:06 编辑

  CELL COMPARISON RESULTS ( TOP LEVEL )

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Different numbers of nets (see below).
  Error: Different numbers of instances (see below).
  Error: Connectivity errors.
  Warning:  Unbalanced smashed mosfets were matched.
  Warning:  Ambiguity points were found and resolved arbitrarily.
  Warning:  LVS property resolution maximum exceeded.

LAYOUT CELL NAME:       chip_finish_final
SOURCE CELL NAME:       pad_top

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:          1110    1110

Nets:       545325 544017 *

Instances:    515610 515266 * MN (4 pins)
            515726 515179 * MP (4 pins)
               331       40 * R (2 pins)
               185       23 * D (2 pins)
            ------ ------
Total Inst: 1031852 1030508

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:          1110    1110

Nets:       276521 274889 *

Instances:    50675    50675       MN (4 pins)
               51276    51276       MP (4 pins)
               100       40 * R (2 pins)
                  19       19       D (2 pins)
                  3       3       SPDW_2_1 (4 pins)
                  8       8       SPDW_2_1_1 (5 pins)
                  7       7       SPDW_2_2 (5 pins)
               518    518       SPDW_2_2_1 (6 pins)
                  1       1       SPDW_3_1 (5 pins)
               19116    19116       SPUP_2_1 (4 pins)
                  2       2       SPUP_2_1_1 (5 pins)
               9267    9267       SPUP_2_2 (5 pins)
                  7       7       SPUP_2_2_1 (6 pins)
               9214    9214       SPUP_2_2_2 (7 pins)
                  36       36       _invb (6 pins)
            114625 114625       _invv (4 pins)
               2622    2622       _invx2v (4 pins)
                  12       12       _invx3v (4 pins)
                  6       6       _invx4v (4 pins)
                  3       3       _invx5v (4 pins)
                  1       1       _invx6v (4 pins)
               28414    28414       _nand2v (5 pins)
                  2       2       _nand3v (6 pins)
                  8       8       _nand4v (7 pins)
               1534    1546 * _nor2v (5 pins)
                  4       4       _nor3v (6 pins)
                  6       6       _nor4v (7 pins)
               130    118 * _pdw2v (4 pins)
                  12       12       _pdw3v (5 pins)
                  9       9       _pup2v (4 pins)
                  12       12       _pup3v (5 pins)
               19121    19121       _sdw3v (5 pins)
               85146    85146       _smn2v (4 pins)
               40151    40103 * _smp2v (4 pins)
                  1       1       _smp3v (5 pins)
                  2       2       _xnor2v (5 pins)
               8221    8221       _xr2v (5 pins)
                  1       1       _xra2v (5 pins)
            ------ ------
Total Inst: 440292 440184

huangbobo · 发表于 2024-10-31 00:07:50

o Statistics: 8 isolated layout nets were deleted. 45075 layout mos transistors were reduced to 18560. 26515 mos transistors were deleted by parallel reduction. 43744 source mos transistors were reduced to 18048. 25696 mos transistors were deleted by parallel reduction. 280 series/parallel layout resistors were reduced to 49. 3 connecting nets were deleted. 183 parallel layout diodes were reduced to 17. 8 parallel source diodes were reduced to 4. 371 source nets had all their pins removed and were deleted. 30947 nets and 50 instances were matched arbitrarily. o Initial Correspondence Points: Ports: VDD VDDPST VSSPST VSS PIX0_VT1_IC PIX0_VT2_IC PIX0_VT3_IC PIX0_VT4_IC PIX1_VT1_IC PIX1_VT2_IC PIX1_VT3_IC PIX1_VT4_IC PIX2_VT1_IC PIX2_VT2_IC PIX2_VT3_IC PIX2_VT4_IC PIX3_VT1_IC PIX3_VT2_IC PIX3_VT3_IC PIX3_VT4_IC PIX4_VT1_IC PIX4_VT2_IC PIX4_VT3_IC PIX4_VT4_IC PIX5_VT1_IC PIX5_VT2_IC PIX5_VT3_IC PIX5_VT4_IC PIX6_VT1_IC PIX6_VT2_IC PIX6_VT3_IC PIX6_VT4_IC PIX7_VT1_IC PIX7_VT2_IC PIX7_VT3_IC PIX7_VT4_IC PIX8_VT1_IC PIX8_VT2_IC PIX8_VT3_IC PIX8_VT4_IC PIX9_VT1_IC PIX9_VT2_IC PIX9_VT3_IC PIX9_VT4_IC PIX10_VT1_IC PIX10_VT2_IC PIX10_VT3_IC PIX10_VT4_IC PIX11_VT1_IC PIX11_VT2_IC o Ambiguity Resolution Points: (Each one of the following objects belongs to a group of indistinguishable objects. The listed objects were matched arbitrarily by the Ambiguity Resolution feature of LVS. Arbitrary matching may be prevented by assigning names to these objects or to adjacent nets). Layout Source ------ ------ Nets ---- X19/X10/X1/32 Xpad_pix_count_resulte_vt2/NET_33 X19/X11/X1/32 Xpad_din/NET_33 X19/X37/12 XVDD1/NET_0 X18/X2829/6 XU3/net6 X18/X2828/6 XU4/net6 X18/X2830/6 XU2/net6 X18/X2826/6 XU5/net6 X18/X2825/6 XU6/net6 X18/X2824/6 XU7/net6 X18/X2834/6 XU12/net6 X18/X2835/6 XU19/net6 X18/X2833/6 XU11/net6 X18/X2836/6 XU13/net6 X18/X2832/6 XU10/net6 X18/X2837/6 XU18/net6 X18/X2831/6 XU9/net6 X18/X2838/6 XU14/net6 X18/X2839/6 XU17/net6 X18/X2840/6 XU15/net6 X19/X4/X1/48 Xpad_move_out/NET_28 X19/X0/X1/48 Xpad_test_mode/NET_28 X19/X7/X1/48 Xpad_rst_n/NET_28 X19/X8/X1/48 Xpad_pix_count_resulte_vt1/NET_28 X19/X10/X1/48 Xpad_test_data/NET_28 X19/X1/X1/48 Xpad_cs_n/NET_28 X19/X6/X1/48 Xpad_clk/NET_28

huangbobo · 发表于 2024-10-31 00:09:20

################################################## ## ## ## C A L I B R E S Y S T E M ## ## ## ## L V S R E P O R T ## ## ## ################################################## REPORT FILE NAME: chip_finish_final.lvs.report LAYOUT NAME: /home/hb23/Projects/tsmc18rf_proj/chip_finish_final.sp ('chip_finish_final') SOURCE NAME: /home/hb23/Desktop/lvs11/20241029lvs/1030_2.sp ('pad_top') RULE FILE: /home/hb23/Projects/tsmc18rf_proj/_calibre.lvs_ CREATION TIME: Thu Oct 31 00:04:05 2024 CURRENT DIRECTORY: /home/hb23/Projects/tsmc18rf_proj USER NAME: hb23 CALIBRE VERSION: v2020.3_16.11 Wed Jul 1 14:09:50 PDT 2020 OVERALL COMPARISON RESULTS # # ##################### # # # # # # INCORRECT # # # # # # # ##################### Error: Different numbers of nets. Error: Different numbers of instances. Error: Connectivity errors. Warning: Unbalanced smashed mosfets were matched. Warning: Ambiguity points were found and resolved arbitrarily. Warning: LVS property resolution maximum exceeded. ************************************************************************************************************** CELL SUMMARY ************************************************************************************************************** Result Layout Source ----------- ----------- -------------- INCORRECT chip_finish_final pad_top ************************************************************************************************************** LVS PARAMETERS *******************************************

Quinn714 · 发表于 2024-10-31 00:57:02

光看错误类型没办法准确判断原因，器件个数对不上有没有可能少画，或者未识别，进而导致net数量不对或者连接存在问题，首先你那个电阻参数能对上不，数量目前来看对不上，还有三个器件个数也对不上，能力有限，再多的光凭目前信息没法判断

[求助] 做LVS时 net和instances

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