finish called from file "/home/pcie_svt/tb_pcie_svt_verilog_basic_sys/tests/ts.test_basic.v", line 364.
$finish at simulation time 103048482.90 ps
V C S S i m u l a t i o n R e p o r t
Time: 103048482900 fs
CPU Time: 2.940 seconds; Data structure size: 14.4Mb
Fri Jul 26 12:38:36 2024