Who can download the phd dissertation?thanks

hardmany

https://utdallas.primo.exlibrisg ... thing&query=any,contains,sar%20adc&offset=40


Details

Title
High speed SAR A/D conversion with digital calibration :




Creator
[url=]Zhou, Yuan (Electrical engineer), author, dissertant. [/url]




Dissertation
Thesis.

Ph. D. The University of Texas at Dallas, 2016.

Chiu, Yun, committee chair.




Subject
[url=]Successive approximation analog-to-digital converters -- Calibration[/url]

[url=]Capacitors[/url]

[url=]Digital-to-analog converters -- Calibration[/url]

[url=]Broadband communication systems[/url]




Summary
Recently, the requirement of direct-sampling receivers in broadband application has been promoting the development of low-power, high-resolution, GS/s rate (GSPS) analog-to-digital converters (ADCs). Conventionally, high-power pipelined ADCs were implemented to realize a conversion speed around 1 GS/s. In this dissertation, we propose several novel techniques to build high-resolution GSPS ADCs using the power-efficient successive-approximationregister (SAR) conversion architecture. This target is accomplished in two steps. Firstly, a 12-bit, high-speed single-channel pipelined SAR ADC is designed to demonstrate a close-to-200MS/s conversion speed with the SAR architecture. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this work to attain high conversion throughput and power savings at the same time using a simple, low-gain ( 30 dB) residue amplifier. The overall architecture and the digital calibration also enable the downsizing of the first SAR stage to that of the kT/C limit, yielding a wideband input network delivering an over 80-dB spurious-free dynamic range (SFDR) while digitizing a 300-MHz input at 160 MS/s. The core ADC consumes 4.96 mW and occupies an area of 0.042 mm2. The ADC achieves a Walden figure-of-merit (FoM) of 20.7 fJ/conversion-step with a Nyquist input. Secondly, a four-way ADC array is implemented by time-interleaving pipelined SAR ADCs to demonstrate 12-bit, 1-GS/s analog-to-digital conversion which can be potentially used in the direct-sampling receiver. Each single channel is a 12-bit, 250-MS/s pipelined SAR ADC. Two digital calibration algorithms are developed to compensate circuit component nonidealities in both the single-channel pipelined SAR ADC and the time-interleaved ADC array. The calibration algorithm treats skew, bandwidth, and static gain, offset errors in this prototype. The prototype time-interleaved (TI) ADC array demonstrates a more than 70-dB SFDR with a 500-MHz input at 1 GS/s. The ADC array achieves a peak signal-to-noise plus distortion ratio (SNDR) of 65.3 dB and consumes 31.5 mW of power. The FoM of the ADC array is 59.7 fJ/conversion-step with a Nyquist input.




Contributor
[url=]The University of Texas at Dallas. Graduate Program in Electrical Engineering, degree granting institution. [/url]




Publisher
Richardson, Texas : The University of Texas at Dallas




Creation Date
2016




Language
English




Physical Description
xv, 96 leaves : illustrations (some color) ; 28 cm

1 online resource : illustrations (some color)

PDF

text file




General Note
Includes vita.




Source
Library Catalog