RISC-V

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Y. Wang, M. Yang, C. -P. Lo and J. P. Kulkarni, "30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 492-494, doi: 10.1109/ISSCC49657.2024.10454387.



K. Li, W. Yin and Q. Liu, "A Portable DSP Coprocessor Design Using RISC-V Packed-SIMD Instructions," 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181681.

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