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发表于 2024-6-15 21:07:43
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不知道在哪里下载这个tessent lab1~9的 运行压缩文档?
多谢!
Lab 9
Tessent Shell EDT Internal RTL Flow
Using Tessent® TestKompress®
Introduction
This lab introduces the internal Tessent TestKompress flow (using Tessent Shell). In
this lab you specify the EDT IP configuration, generate the EDT IP, insert RTL into
the Verilog netlist, and generate the script needed for synthesis.
You inserts EDT logic into the core netlist using the command and argument
write_edt_files -insertion tk.
EDT Tool Flow
In this lab you use the scripts provided to walk through scan chain insertion using
Tessent Scan, and pattern generation using Tessent TestKompress. For the EDT
insertion phase, you enter command at the tool’s SETUP prompt. Using commands
instead of scripts the first time you create EDT IP helps you to learn the process and
understand the flow. During EDT IP creation, synthesis scripts are generated, along
with an EDT-specific test procedure file and dofile.
Pattern generation is run on the version of the design that has been synthesized. You
will notice that the commands for pattern generation for TestKompress are the same
as those used for Tessent FastScan.
Design
In this lab you start with a non-scan Verilog gate level netlist implementation of the
Microchip PIC 16CCC5X micro controller.
Compression Results
In general, the compression ratio is equal to the number of internal scan chains
divided by the number of external scan channels. This ratio affects the way that the
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