rapid io 4.0 controller

_Jassica

if anyone interested to buy, contact me through mail.

226276875@qq.com


Attached is  partial GRIO Datasheet.


Key Feature
• Implements Logical, Common Transport and Physical layers
• Supports Part 1: Input/Output Logical Specification, Revision 4.0
• Supports Part 2: Message Passing Logical Specification, Revision 4.0
• Supports Part 3: Common Transport Specification, Revision 4.0
• Supports Part 4: Physical Layer 8/16 LP-LVDS (parallel interface) Specification, Rev 1.3
• Supports Part 5: Globally Shared Memory Logical Specification1, Rev 4.0
• Supports Part 6: LP-Serial Physical Layer Specification, Revision 4.0
• 1x, 2x, 4x, 8x and 16x2 ports
• 1.25 Gbaud, 2.5 Gbaud, 3.125 Gbaud and 5 Gbaud lane rates (BRC 1)
• 6.25 Gbaud lane rate (BRC 2)
• 10.3125 Gbaud, 12.5 Gbaud and 25.78125 Gbaud lane rate (BRC 3)
• CS24 (Short Control), CS48 (Long Control) and CS64 Control Symbols
• Scrambling and De-scrambling
• IDLE2 Sequence and Adaptive Equalization (lane training)
• IDLE3 Sequence, Lane training and re-training, Asymmetric and Time-synchronization3
• Supports Part 7: System and Device Inter-operability Specification, Revision 4.0
• Supports Part 8: Error Management Extensions Specification, Revision 4.0
• Supports Part 9: Flow Control Logical Layer Extension Specification, Revision 4.0
• Supports Part 10: Data Streaming Logical Specification, Revision 4.0
• Supports Part 11: Multicast Extensions Specification, Revision 4.0
• Supports external configuration master, accessing GRIO configuration registers through the
PBUS interface.
• Architectured for high link utilization and low latency
• Efficient receive and transmit buffering scheme
• Implements receiver controlled flow control
• Supports up to 256 Bytes data payload
• Supports acknowledging multiple packets4
• Provides packet based user logic interface
• Supports hardware error recovery