UCIE CTRL + PHY N3

_toroto

Hi eetopians,
let me introduce myself to all, i'm Billy (_toroto) , from northern part have 10+ years of experience in semicondustor industry


UCIE CTRL:- General Product Description
The UCIe controller provides a solution to implement the Universal Chiplet Interconnect express (UCIe) Die-to-Die (D2D) Adapter and Protocol Layer. UCIe is an open, multi-protocol capable, and on-package interconnect standard for connecting multiple dies on the same package. UCIe supports multiple Protocol Layers (PCIe 5.0 or PCIe 6.0, CXL 2.0 or CXL 3.0, and Streaming Protocol Layers to map any protocol of choice if both dies support such a mapping) on ​​​​top of a common Physical and Link Layer.
The UCIe controller and its associated Logical Physical Layer provide a framework for low power, low latency, and high bandwidth electrical signaling between the dies, over multiple substrate types. Among many other use cases, the Die-to-Die UCIe connectivity enables the system integrator to:
1. Split processing the dies to increase the computing power.
2. Disaggregate I/O die from the central processing die, enabling the processing die to migrate to more
advanced nodes.
3. Integrate multiple homogeneous and heterogeneous components, enabling systems to scale up and
extend Moore's Law.
4. Aggregate dies for specific functions and technology nodes using UCIe connection.
5. Achieve flexibility in terms of its data rate and overall bandwidth.
6. Create low latency, low power, and reliable (using CRC and Retry) systems.




UCIE PHY:- DWC UCIe 4TA4 NS TSMC N3EP
General Product Description
The D2D UCIe solution consists of the PHY Utility Block (PUB) soft IP and the PHY hard macro IPs. The PUB provides control features to ease the customer implementation of digitally controlled features of the PHY such as initialization , lane repair, training, delay line calibration and VT compensation. The PUB has built-in self-test features to provide support for production testing of the PHY. It also provides the UCIe Raw Die-to-Die Interface (RDI) to the PHY.



Synopsys IP UCIe PHY supports the following features:
◼ UCIe operation compatible with Universal Chiplet Interconnect Express (UCIe) standard up to 16GT/s.
◼ Product hardened components (MMX1/MMPL) to precisely control timing critical delay and skews.
◼ Includes PLL and Digital Delay Lines necessary to meet timing specifications.
◼ Support for up to 16 modules per MMPL (maximum 8 of modules on either side of the MMPL). An unequal number of MMX1 modules on the left and MMX1M modules on the right of MMPL is supported for certain configurations. Refer to the Synopsys IP UCIe PHY Utility Block (PUB) Databook for the supported floorplans
◼ Maximum RDI clock frequency of 2000 MHz resulting in maximum PHY data rate of 16,000 MT/s.
◼ At-speed built-in-self-test (BIST) loopback testing.
◼ Delay line oscillator test mode.
◼ Mux-scan ATPG.
◼ Training for read latency, strobe position, per bit deskew, and VREF.
◼ Automatic IO impedance and On-Die termination calibration using a 25 ohm external resistor (+/-2 ohm for all parasitic and impedance variation).
◼ Support anti- aging if the PHY is more than two months in idle mode.
◼ PHY Utility Block (PUB), includes PHY control features, such as initialization, and provides support for production testing of the Synopsys IP UCIe PHY (Refer to the Synopsys IP UCIe PHY Utility Block (PUB) Databook).




if anyone interested to buy, contact me through mail
3667626117@qq.com


looking forward to connect with everyone

--Billy