xcelium L2E_2错误

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这些都按多个教程里，改好vsup vlo vthi

但错误始终有

Simulation Error:
The simulator process returned a non-zero exit code, indicating failure.
The simulator could have crashed or intentionally returned to indicate an error.
Check the simulator log file for more information.  Common causes:
1. Simulator may have crashed during exit even after reporting success in log file.
2. Abrupt automatic simulator termination (e.g., SIGKILL) because the simulator process has
   exceeded resource limits, which can be specified in the distribution system or
   by the kernel itself (e.g., the Linux OOMKiller).
3. Manual termination of the simulator process.
./runSimulation can be manually run in this directory to check the issue.

csi-xmsim - CSI: Cadence Support Investigation, recording details
External Code in function: <unavailable> offset -65518
External Code in function: <unavailable> offset -65536
Intermediate File: string (IF_STRING) in snapshot abc.invv_tb:config (SSS)
        Decompile: net1__E2L_2__logic
Verilog Syntax Tree: register declaration (VST_D_REG) in module connectLib.L2E_2:module (VST)
        File: /home/xyz/cadence/XCELIUM2303/tools/affirma_ams/etc/connect_lib/L2E_2.vams, line 104, position 14
        Scope: L2E_2
        Decompile: real tdelayvar
        Source  :  real tdelayvar;                // variable delay
        Position:               ^
Verilog Syntax Tree: real type (VST_T_REAL) in module connectLib.L2E_2:module (VST)
        Decompile: real
Verilog Syntax Tree: overlay table (VST_OVERLAY_TABLE) in module connectLib.L2E_2:module (SIG) <0x71ae6e41>
        Decompile: L2E_2#(vsup,vlo,vhi,vthi,vtlo,vx,tr,tf,ttol_t,tdelay,tdeltran_fall,rhi,rlo,rz,rx,debug,vinlimit,r_SUPPLY,r_STRONG,r_PULL,r_LARGE,r_WEAK,r_MEDIUM,r_SMALL,has_delay)
Verilog Syntax Tree: module declaration (VST_D_MODULE) in module abc.invv_tb:schematic (VST)
        File: /home/xyz/simulation/abc/invv_tb/maestro/results/maestro/ExplorerRun.0/1/abc_invv_tb_1/netlist/netlist.vams, line 24, position 13
        Scope: invv_tb
        Decompile: invv_tb
        Source  : module invv_tb ( );
        Position:              ^
Error: Error processing stack frame(12) - skipping rest of frame!
External Code in function: <unavailable> offset -65534
Simulator Snap Shot: autoinst ams (SSS_AMS_AUTOINST) in snapshot abc.invv_tb:config (SSS)
Error: Error processing stack frame(14) - skipping rest of frame!
Internal Code in function: %d) - skipping rest of frame!
offset 1307674956
External Code in function: <unavailable> offset -65535
External Code in function: <unavailable> offset -64536
Verilog Syntax Tree: module declaration (VST_D_MODULE) in module connectLib.L2E_2:module (VST)
        File: /home/xyz/cadence/XCELIUM2303/tools/affirma_ams/etc/connect_lib/L2E_2.vams, line 71, position 18