calibre PEX中gate level 和transistor level区别

oldwy

目前觉得简而言之可以说模拟选transistor 数字选gate


一个有趣的东西：
Biasingover 7 years ago

Is there any fundamental difference between gate level extraction and transistor level extraction?

And in calibre xRC toolkit, what does C and CC represent for ?C means the parasitic to the substrate? and CC means the parasitic to the nets?

Best regards,

Mingliang

Andrew Beckettover 8 years ago

Mingliang,

You might want to look at the logo at the top of this page - it shows "Cadence". Look for the logos you see when using Calibre - you'll see they say "Mentor Graphics". Different company - Cadence's physical verification tools are PVS, Assura, Dracula, Diva (plus a couple of others) - Calibre is not our tool and so this is not really the best place to ask about a tool from a different company!

However, your questions are pretty generic. Gate level extraction just means that you treat the gates (standard cells) as black boxes and extract the parasitics for the interconnect; often this is done from a DEF description of the layout. Transistor level extraction would be combined with LVS and would extract the devices and all the parasitics around the devices too as well as the interconnect.

In Calibre terminology, C means lumping the capacitance to ground, whereas CC means extracting the coupled capacitance between nets. You end up with more capacitors that way and it can be slower to simulate because you have a more dense matrix to be solved as there are more interactions to be solved.

This is all answered without real knowledge of Calibre though - I don't have access to it as an employee of a competing EDA company!

Regards,

Andrew.

Biasingover 8 years ago

Hi Andrew,

I am so sorry for the mistake. Maybe I should have a try to use Assura, then I can ask you more....

Thanks a lot for answer the "LOST" question....

Best regards,

Mingliang

翻译：

偏置

7年多前

门级提取和晶体管级提取之间有什么根本区别吗？

在calibre xRC工具包中，C和CC代表什么？C表示对衬底的寄生？ CC是指寄生到网络吗？

此致，

明亮

安德鲁·贝克特

8年多前

明亮,

您可能想查看此页面顶部的徽标 - 它显示“Cadence”。 查找您在使用 Calibre 时看到的徽标 - 您会看到它们写着“Mentor Graphics”。 不同的公司 - Cadence 的物理验证工具有 PVS、Assura、Dracula、Diva（加上其他几个） - Calibre 不是我们的工具，因此这并不是询问其他公司工具的最佳位置！

然而，你的问题很笼统。 门级提取只是意味着将门（标准单元）视为黑匣子并提取互连的寄生效应； 通常这是通过布局的 DEF 描述来完成的。 晶体管级提取将与 LVS 相结合，并提取器件以及器件周围的所有寄生效应以及互连。

在 Calibre 术语中，C 表示将电容集中到地，而 CC 表示提取网络之间的耦合电容。 这样你最终会得到更多的电容器，并且模拟速度可能会更慢，因为需要解决的矩阵更密集，因为有更多的相互作用需要解决。

不过，这一切都是在没有真正了解 Calibre 的情况下得到的答案 - 作为竞争 EDA 公司的员工，我无法访问它！

问候，

安德鲁。

偏置

8年多前

嗨安德鲁，

我对这个错误感到非常抱歉。 也许我应该尝试使用阿修罗，然后我可以问你更多......

非常感谢您回答“丢失”问题......

此致，

明亮

oldwy

再问问gpt：

what is the difference between transistor level and gate level in PEX

ChatGPT

In the context of Physical Design Automation (PDA) tools like PEX (Physical Extraction), "transistor level" and "gate level" refer to different levels of abstraction used in the representation of a digital circuit.



Transistor Level:



At the transistor level, the circuit is represented using individual transistors and their interconnections.

This level of abstraction provides a detailed and fine-grained representation of the digital circuit, including the individual transistors that make up logic gates and other components.

Transistor-level representations are closer to the physical implementation of the circuit, making them suitable for detailed analysis of electrical characteristics, power consumption, and other physical properties.

PEX tools at the transistor level deal with extracting physical information such as parasitic capacitances, resistances, and other transistor-level details.

Gate Level:



At the gate level, the circuit is represented using logic gates (e.g., AND, OR, NAND, NOR) and their interconnections, without detailing the individual transistors within each gate.

This level of abstraction is higher than the transistor level and is often used for tasks like logical synthesis and optimization.

Gate-level representations provide a more abstract and compact view of the circuit, making them suitable for design exploration, optimization, and higher-level analysis.

PEX tools at the gate level primarily focus on extracting information related to logic connectivity and parasitics associated with the gates, rather than individual transistors.

In the PEX context, the goal is to extract various physical and electrical characteristics from the layout of a digital circuit. Depending on the specific requirements and goals of the analysis, PEX tools may operate at different levels of abstraction. Transistor-level extraction is more detailed and accurate but can be computationally intensive, while gate-level extraction provides a faster analysis with a higher level of abstraction. The choice between transistor and gate level depends on the specific needs of the analysis or optimization being performed.



翻译：

PEX中晶体管级和门级有什么区别



聊天GPT



在 PEX（物理提取）等物理设计自动化 (PDA) 工具的背景下，“晶体管级”和“门级”是指数字电路表示中使用的不同抽象级别。







晶体管电平：







在晶体管级别，电路使用单独的晶体管及其互连来表示。



这种抽象级别提供了数字电路的详细且细粒度的表示，包括构成逻辑门和其他组件的各个晶体管。



晶体管级表示更接近电路的物理实现，使其适合对电气特性、功耗和其他物理属性进行详细分析。



晶体管级的 PEX 工具负责提取物理信息，例如寄生电容、电阻和其他晶体管级细节。



门级别：







在门级，电路使用逻辑门（例如 AND、OR、NAND、NOR）及其互连来表示，而没有详细说明每个门内的各个晶体管。



这种抽象级别高于晶体管级别，通常用于逻辑综合和优化等任务。



门级表示提供了更抽象和紧凑的电路视图，使其适合设计探索、优化和更高级别的分析。



门级 PEX 工具主要侧重于提取与逻辑连接和与门相关的寄生相关的信息，而不是单个晶体管。



在 PEX 环境中，目标是从数字电路的布局中提取各种物理和电气特性。 根据分析的具体要求和目标，PEX 工具可以在不同的抽象级别上运行。 晶体管级提取更加详细和准确，但计算量较大，而门级提取提供了更快的分析和更高的抽象级别。 晶体管和门级之间的选择取决于所执行的分析或优化的具体需求。



再看看实例：

来源于《CMOS模拟集成电路版图设计与验证-基于Cadence Virtuoso与Mentor Calibre【电子工业出版社201609】尹飞飞》

oldwy

再看看实例：

来源于《CMOS模拟集成电路版图设计与验证-基于Cadence Virtuoso与Mentor Calibre【电子工业出版社201609】尹飞飞》