Behavioral Model for High-Speed SAR ADCs With On-Chip References
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https://ieeexplore.ieee.org/document/10286528 A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier
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https://ieeexplore.ieee.org/document/10258404 A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation
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https://ieeexplore.ieee.org/document/10296839 A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads