PLL5GHz N16

ipseller

1.1 General Product Description
his clock-multiplying PLL macro-cell is designed for a TSMC 16nm FFC CMOS technology. The PLL
opology has an analog loop with a ring oscillator in its core.
he PLL has 2 independent output clock channels (R and P) , and each channel frequency is obtained
rom a programmable integer division of the VCO operating frequency. Each output channel division
alue is the result of a multiplication between two factors, from two different divider values, and the
otal division ranges from 2 to 4096.
he VCO output frequency is also divided by Fractional Division Circuit (ranging from 16 to 1039) before
eing compared to an input, which in turn can be an integer division (from 1 to 32) of a crystal based,
eference input frequency.
A built- in gearshift mode during startup promotes faster locking times at the expense of higher jitter at
tartup or relock phases, but aims locking times below 10µs.


1.2 Product Features
he PLL provides the following features:
■ TSMC16FFC CMOS technology
■ Fully integrated, compact design
■ 1.8 V analog, 0.8V digital supply
■ VCO oscillating range 2.5-6.0 GHz
■ Loop comparison frequency 20-150 MHz
■ Output frequency range 0.61-3000 MHz
■ Individually controlled output clocks by means of 2 output-dividers
■ PLL core bypass mode
■ PLL gear-shift mode to decrease locking time (<10µs)
■ LT Jitter lower than 2.9ps rms for a VCO @5GHz and a Ref @ 50MHz
■ ~6.9mA current consumption from the analog supply
■ ~3.9mA current consumption from the digital supply
■Area 0.051 mm 2

Deliverables:
gds
timing
behavior
lef
ipxact
upf
testbench
spyglass
caliber
atpg
sim
interface
icv
netlist


to Buy:-
Contact:    ipseller@tutamail.com