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case_analysis_propagate_through_icg 的description如下
When this variable is set to false (the default), constants propagating throughout the design will stop propagating when anintegrated clock gating cell is encountered. Regardless of whether the integrated clock gating cell is enabled or disabled, no logicvalues will propagate in the fanout of the cell.
When the value is true, constants propagated throughout the design will propagate through an integrated clock gating cell, providedthe cell is enabled. An integrated clock gating cell is enabled when its enable pin (or test enable pin) is set to a high logic value. Ifthe cell is disabled, then the disable logic value for the cell is propagated in its fanout. For example, for a latch_posedge ICG, whenit is disabled, it will propagate a logic 0 in its fanout.
那么在默认false的时候,无论enabled还是disabled,clk都会穿过ICG么
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