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发表于 2023-5-26 13:23:22
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要在电路级别用SPICE类型的仿真器(比如spectre)仿真ESD电路的前提条件是需要有ESD器件放电的宏模型;因为PDK中提供的SPICE器件模型通常只对正常工作区域进行了建模,没有对ESD大电流放电的情况进行建模,因此很难直接用了验证ESD电路设计的好坏。
以下这篇文献提出了基于宏模型的仿真方案,可以参考一下试试。
[1] F. Zhang et al., ‘A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models’, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 3, pp. 489–498, Mar. 2019, doi: 10.1109/TCAD.2018.2818707.
Full-chip electrostatic discharge (ESD) protection circuit design verification is needed for complex ICs at advanced technology nodes despite being largely impractical due to the limitation of ESD device models and CAD tools. This paper reports a new circuit-level ESD protection design simulation and dynamic checking method using SPICE and ESD device behavior models which allows comprehensive, quantitative, and dynamic verification of ESD protection circuit designs at chip level-based entirely on ESD discharging functions. The new ESD protection circuit simulation method is validated using ICs designed and fabricated in a 28 nm CMOS. This ESD-function-based ESD circuit simulation method is technology independent, which can handle various ICs including complex multiple power domain circuits and ICs using nontraditional ESD protection structures.
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