Design on Mixed-Voltage I/O Buffers

semico_ljj

Design on Mixed-Voltage I/O Buffers
with Consideration of Hot-Carrier Reliability

Ming-Dou Ker and Fang-Ling Hu

Nanoelectronics and Gigascale Systems Laboratory
Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan

Abstract   
A new circuit design for mixed-voltage I/O buffers
to prevent hot-carrier degradation is proposed. The mixedvoltage
(2xVDD tolerant) I/O buffer is designed with hotcarrier-
prevented circuits in a 0.18-􀈝m CMOS process to
receive 3.3-V (2xVDD tolerant) input signals without suffering
gate-oxide reliability, circuit leakage issues, and hot-carrier
degradation. In the experimental chip, the proposed mixedvoltage
I/O buffer can be operated with signal speed of up to
266 MHz, which can fully meet the applications of PCI-X 2.0.

semico_ljj

In this paper, a novel circuit design (called as hot-carrierprevented
circuit) is proposed to solve hot-carrier reliability
issue in the 2xVDD-tolerant I/O buffers with two-stacked
transistors. The driving ability of the new proposed 2xVDDtolerant
I/O buffer can be kept the same as that of the
original mixed-voltage I/O buffer with the same device
dimensions.

semico_ljj

CONCLUSION
A new 2xVDD-tolerant I/O buffer with hot-carrierprevented
circuits has been successfully verified in a 0.18-um 1.8-V
CMOS process with only thin-oxide devices. The
drain-source voltages of transistors in the 2xVDD-tolerant
I/O buffer can be kept within the normal operating voltage
range (VDD) by the proposed hot-carrier-prevented circuits.
This new 2xVDD-tolerant I/O buffer can be operated up to
266MHz to receive 1.5-V/3.3-V input signals or to transmit
the 1.5-V output signals, which can meet the high-speed I/O
applications of PCI-X 2.0.

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