ESD Robustness of High-Voltage NMOS（40V）：Ming-Dou Ker

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The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process

Wei-Jen Chang1, Ming-Dou Ker1, Tai-Xiang Lai2, Tien-Hao Tang2, and Kuan-Cheng Su2
1Nanoelectronics and Gigascale Systems Laboratory
Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
2United Microelectronics Corp., Science-based Industrial Park, Taiwan

Abstract
The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

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Conclusion
The N-drift implant in the drain region and layout spacing (D) from the drain diffusion to polygate have been spilt to verify the ESD robustness of HV NMOS and HVNSCR in a given 40-V CMOS process. It has been found that the devices without N-drift implant have higher TLP-measured It2 than those with N-drift implant. For HVNSCR, the TLP-measured It2 can be improved over 6A by removing N-drift in the drain region. Due to the different current distributions in HV GGNMOS and HVNSCR, the dependences of TLP-measured It2 on the spacing of D are different.


Acknowledgment
The first author was supported by the MediaTek Fellowship, Hsinchu, Taiwan.

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Double Snapback Characteristics in High-Voltage
nMOSFETs and the Impact to On-Chip
ESD Protection Design

Ming-Dou Ker, Senior Member, IEEE, and Kun-Hsien Lin, Student Member, IEEE

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Abstract—The double snapback characteristic in the highvoltage
nMOSFET under transmission line pulsing stress is found.
The physical mechanism of double snapback phenomenon in the
high-voltage nMOSFET is investigated by device simulation.With
double snapback characteristic in high-voltage nMOSFET, the
holding voltage of the high-voltage nMOSFET in snapback breakdown
condition has been found to be much smaller than the power
supply voltage. Such characteristic will cause the high-voltage
CMOS ICs susceptible to the latchup-like danger in the real
system applications, especially while the high-voltage nMOSFET
is used in the power-rail electrostatic discharge clamp circuit.


Index Terms—Double-diffused drain (DDD), electrostatic discharge
(ESD), high-voltage nMOSFET, lateral diffused MOS
(LDMOS), latchup.

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CONCLUSION
The double snapback characteristic in the high-voltage
nMOSFET has been investigated in this work. With both
measured and simulation results, the double snapback characteristics
in the 18-V and 40-V nMOSFETs have been fully
analyzed. The latchup-like issue between the power rails in the
high-voltage CMOS ICs has been confirmed by TLU test. How
to avoid the latchup-like failure of high-voltage nMOSFET
under normal circuit operating condition will be an important
challenge to on-chip ESD protection design for high-voltage
CMOS IC products.

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