tetramax basic scripts

HLDDTOP

set_messages -log mylog -replace
# Read in the netlist library and
# Verilog library 标准单元库文件和设计文件
read_netlist -library library/*.v
read_netlist design.v
# Build the ATPG Model
run_build_model DESIGN_TOP
# Set up and run DRC建立并运行DRC
set_drc stil_procedures.spf
run_drc
# Add faults and run ATPG 加入故障并运行ATPG
add_faults -all
run_atpg -auto
# Write the patterns 写入pattern
write_patterns DESIGN.stil -format STIL \
  -replace
write_patterns DESIGN.bin -replace
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版权声明：本文为CSDN博主「数字IC新人小白」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/qq_34882285/article/details/123519603

HLDDTOP

Basic ATPG设计流程包含以下步骤：

1. Prepare your netlist or netlists.
2. Read the netlist.
3. Read the library models.
4. Build the ATPG design model.
5. Perform test DRC and make any necessary corrections.
6. Prepare the design for ATPG, set up the fault list, analyze buses for contention, and set
the ATPG options.

7. Run automatic test pattern generation .
8. Analyze the ATPG pattern generation output.
9. Review the test coverage .
10. Rerun ATPG, as needed.
11. Write and save the test patterns.
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版权声明：本文为CSDN博主「数字IC新人小白」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/qq_34882285/article/details/123519603