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By Shivakumar Chonnad, Needamangalam Balachander,
- Publisher: Springer
- Number Of Pages: 238
- Publication Date: 2004-09-23
- Sales Rank: 742878
- ISBN / ASIN: 0387228349
- EAN: 9780387228341
- Binding: Hardcover
- Manufacturer: Springer
- Studio: Springer
- Average Rating: 4.5
- Total Reviews: 3
Book Description:
Thisbook addresses "front end" questions and issues encountered in usingthe Verilog HDL, during all the stages of Hardware Design, Synthesisand Verification. The issues discussed in the book are typicallyencountered in both ASIC design projects as well as in Soft IP designs.These issues are addressed in a simple Q&A format. Since each issueis independently dealt with and explained in detail, this book acts asan important source of reference for the Verilog users. Each of theFAQs will be illustrated with figures and tables as required. Thelatest Verilog-2001 and SystemVerilog have also been referred to inthis book.
With the increasing complexity of ASICs beingdesigned these days, the decisions that one makes in any of the stagesof Design, Synthesis or Verification has profound effects on thesethree stages. This book presents the intricacies of theseinter-dependent issues in the context of the Verilog HDL.
Date: 2005-09-22 Rating: 4
Review: Very good Verilog and hardware design book
Thisbook tries to do three things: 1) introduce designers to some of theidiosynchrasies and pitfalls of the Verilog language, 2) teach someimportant basic digital design principles, and 3) go beyond purefunctionality and help designers appreciate testability, verification,and emergent system performance issues. It does very well in all, Ithink. They do not mire themselves down in the detailed syntax orsemantics of Verilog except in avoiding the aforementioned pitfalls. Onthe whole, the design principles are well illustrated. They didreference a web page on metastability and synchronization between clockdomains, but by and large, the book is self contained. It seems to methat there is an error in the gated clock discussion in Fig. 2.20. Theclock polarity is invered compared with Fig. 2.19 - the latter iscorrect. Also ~clk needs to be used instead of clk in some of the latchcontrol code in the corresponding Verilog examples. Otherwise, I havefound few problems. This book is by far the best of the dozen or so(generally poor) Verilog books I have read.
Date: 2005-05-15 Rating: 5
Review: Excellent Book for verilog users
Istarted writing in verilog HDL in early 1990. When I read this book itgives me lot of of new information that I was not aware of. Fromstudents to senior engineers, I strongly suggest to read this book. Itprovides very good tips to write your code for synthesis andverification. Again, excellent book.
Regards,
VerilogGeek
Date: 2005-01-12 Rating: 5
Review: Highly recommend!
Ihighly recommend this book for students/engineers who have basicknowldges in Verilog and want to know how to improve their design andwhat they should focus on during their design phase for their project.
This book is well-organized. It starts from basic concept ofverilog, followed by the RTL design, and verification. The authors evenprovides a section called common mistakes to help readers understandthe pitfalls they usually make and the side effect of making thesemistake.
This book is easy to read. One of the reasons is the authorsprovide a very good flow for readers to read through the book (frombasic to advanced); moreover, the authors also provide explanation forsome jargons which beginners are not familiar with. Finally, all of thequestions are listed in TOC, which is pretty easy forstudents/engineers to skip to the topics which interest them.
I believe this book is a must-have in the book shelf. For students,you may ask your library to buy this since it is not cheap. However, itdoes worth buying if you want to keep it yourself.
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