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第一篇
Design of Multi-bit Sigma Delta Modulators for Digital Wireless Communications
Royal Institute of Technology, in partial fulfillment of the
requirements for the degree of Doctor of Technology.
The ever advance of CMOS digital circuit process leads to the trend of digitizing an
analog signal and performing digital signal processing as early as possible in a signal
processing system, which in turn leads to an increasing requirement on analog-to-digital
converter (ADC). A wireless transceiver is a such kind of signal processing system.
Conventional transceivers manipulate (filter, amplify and mix) the signal mostly
in analog domain. Since analog filters are difficult to design on-chip, the system integration
level is low. Modern transceivers shift many of these tasks to digital domain,
where the filtering and channel selection can be realized more accurately and more
compactly. However the price for the high integration level is the critical requirement
on the ADC, because the simplified analog part sends not only the weak signal but also
the unwanted strong neighboring channel to the ADC. In order to digitize the needed
signal in the presence of strong disturbances, a high dynamic-range and high-speed
ADC is needed.
第二篇 大師之作
High-Speed, Low-Power Sigma-Delta Modulators for RF
University of California, Berkeley
Author: Arnold R. Feldman
Chairman of Committee: Paul R. Gray
第三篇
Quadrature Bandpass Delta-Sigma
Auther: Stephen Andrew Jantzi
Graduate Department of Electrical and Computer Engineering University of Toronto
Abstract:
Considerable research effort in the field of microelectronics pushes towards the realization of
fully monolithic, chiefly digital, RF transceivers — with the ultimate objective being the
implementation of small, inexpensive, low-power communication devices that are robust,
testable, and capable of handling multiple communications standards. Two-path zero-IF
architectures and single-path bandpass-ΔΣ-based architectures strive to attain these dual goals,
but neither effectively achieves both.
This thesis proposes a low-IF receiver architecture, which, with modern quadrature imagereject
mixers and strategic IF placement, offers a viable solution for realizing digital, monolithic
receivers. A critical, and heretofore non-existing, component of such a system — and indeed of
any receiver that uses image-reject mixing to alleviate off-chip filtering requirements — is one
that efficiently performs bandpass A/D conversion on quadrature signals.
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