TSV 3D RF Integration High Resistivity Si Interposer Technology @2022

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    This book presents the preliminary research accomplishments achieved by our research group over the past 10 years with respect to the high-resistivity (HR) Si inter- poser applied to 3D heterogeneous RF integration. This includes fundamental research on the HR-Si interposer design and process validation, which aims at addressing the core problem of high-frequency loss, new 3D RF interconnection structure design and pro- cess validation based on the HR-Si interposer, and application and verification with 3D RF heterogeneous integration to demonstrate its feasibility and technical advantages. In order to elevate the integration level, an HR-Si interposer integrated inductor and inte- grated patch antenna on stacked HR-Si interposer were studied. Given the heat dissipa- tion problem of high-performance TR integration, an HR-Si interposer with an embedded microchannel was investigated and validated with a 2–6 GHz GaN HEMT- based power amplifier. TGV interposer technology is also reviewed along with research and development advancements in TGV formation, metallization, TGV-enabled IPDs, and glass-based embedded wafer level packages. TGV interposer-based 2.5D/3D RF integration by Professor Daquan Yu and my team is presented, to provide a full view of interposer technology for 3D RF integration.

    Several books in English are available to readers on the “more than Moore” (MtM) electronics packaging. However, most of them are limited to the conceptualization of integration or package architecture, electrical, and process evaluation. This book focuses on a specific topic: a 3D heterogeneous RF integration oriented HR-Si and TGV inter- poser from our research, with the intention of reviewing the progress in this field to communicate with researchers who have interests or will be engaged in the related tech- nology areas. Constructive suggestions or criticisms are appreciated, in hopes of putting forward the advances in this field.

    This book is intended for design engineers, processing engineers, and application engineers as well as for postgraduate students majoring in advanced electronics packaging.

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