Efficient Design of Variation-Resilient Ultra-Low Energy @2021

2046 · 发表于 2022-10-31 22:53:40

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This book describes the continuation of the work in the KU Leuven-MICAS division on ultra-low energy processors. In previous work (Reynders N., Dehaene W., Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits, Springer, 2015), we showed that using transmission gates can result in variation-resilient energy- efficient digital signal processing blocks. However, at that time, these techniques could only be used in a handcrafted way on relatively regular data paths. Besides further optimizing the circuit techniques, we take this technique a step further in this work. Our transmission gates end up in a library that is compatible with regular digital design flows. An extension to the flow, to deal with the differential nature of the transmission gate-based logic, is also described. This results in an ARM Cortex- M0 as a demonstrator of the excellent energy efficiency these techniques allow.

The circuits presented run at a supply voltage below 500 mV. This calls for large design margins, even if intra-die variability is properly dealt with. These margins are canceling part of the energy improvements that comes with low power supply voltages. To deal with this, we introduce in situ timing detection in the system. Late transitions on paths with small timing slack are detected, and by means of special soft-edge flip-flops, timing errors are avoided. This results again in an ARM Cortex- M0 which can now be operated at very low energy without the need for large margin on the power supply.

This book is the result of 5 years of PhD work: a close cooperation between a young researcher and his advisor. As you will read, it was a very fruitful cooperation which we enjoyed a lot. We hope that sharing our results with you also brings you the professional achievements you strive for.