Computer Organization and Architecture Designing for performance, Global Edition, 11th Edition (William Stallings)

2046

The most noteworthy changes are as follows:

■■ Multichip Modules: A new discussion of MCMs, which are now widely used, has been added to Chapter 1.

■■ SPEC benchmarks: The treatment of SPEC in Chapter 2 has been updated to cover the new SPEC cpu2017 benchmark suite.

■■ Memory hierarchy: A new chapter on memory hierarchy expands on material that was in the cache memory chapter, plus adds new material. The new Chapter 4 includes:

—Updated and expanded coverage of the principle of locality

—Updated and expanded coverage of the memory hierarchy

—A new treatment of performance modeling of data access in a memory hierarchy

■■ Cache memory: The cache memory chapter has been updated and revised. Chapter 5 now includes:

—Revised and expanded treatment of logical cache organization, including new figures, to improve clarity

—New coverage of content-addressable memory

—New coverage of write allocate and no write allocate policies —A new section on cache performance modeling.

■■ Embedded DRAM: Chapter 6 on internal memory now includes a section on the increasingly popular eDRAM.

■■Advanced Format 4k sector hard drives: Chapter 7 on external memory now includes discussion of the now widely used 4k sector hard drive format.

■■Boolean algebra: The discussion on Boolean algebra in Chapter 12 has been expanded with new text, figures, and tables, to enhance understanding.

■■Assembly language: The treatment of assembly language has been expanded to a full chapter, with more detail and more examples.

■■Pipeline organization: The discussion on pipeline organization has been substantially expanded with new text and figures. The material is in new sections in Chapters 16 (Processor Structure and Function), 17 (RISC), and 18 (Superscalar).

■■Cache coherence: The discussion of the MESI cache coherence protocol in Chapter 20 has been expanded with new text and figures.

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