在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 1866|回复: 5

[资料] 高压集成电路中的衬底耦合效应

[复制链接]
发表于 2022-8-19 14:10:05 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
[Analog Circuits and Signal Processing] Pietro Buccella, Camillo Stefanucci, Mah.pdf (7.87 MB, 下载次数: 70 )
978-3-319-74382-0.jpg
Title: Parasitic Substrate Coupling in High Voltage Integrated Circuits Edition: 1st ed.
Author(s): Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
Publisher: Springer
Year: 2018
Pages: XVII, 183
DOI owner: Springer-Verlag
Language:English
Crossref Book ID:B3009528
Tags:Circuits and Systems; Electronic Circuits and Devices; Electronics and Microelectronics, Instrumentation; Engineering
book

Edition ID: 138027615
Added: 2018-08-15 07:07:45
Modified: 2022-04-09 09:40:24








This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.
The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.
The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.
Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
[...]


Front Matter ....Pages i-xvii
Overview of Parasitic Substrate Coupling (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 1-9
Design Challenges in High-Voltage ICs (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 11-39
Substrate Modeling with Parasitic Transistors (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 41-68
TCAD Validation of the Model (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 69-96
Extraction Tool for the Substrate Network (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 97-112
Parasitic Bipolar Transistors in Benchmark Structures (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 113-143
Substrate Coupling Analysis and Evaluation of Protection Strategies (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 145-174 [...]



发表于 2022-8-19 21:39:06 | 显示全部楼层
kanakna
发表于 2022-8-20 13:23:10 | 显示全部楼层
下载看看
发表于 2022-8-20 20:30:19 | 显示全部楼层
谢谢分享
发表于 2023-10-8 18:19:07 | 显示全部楼层
谢谢分享这么好的资料
发表于 2023-10-18 09:27:25 | 显示全部楼层
针对高压集成电路的衬底耦合效应,非常不错
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条


小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-12-25 13:46 , Processed in 0.018563 second(s), 7 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表