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[资料] 高压集成电路中的衬底耦合效应

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发表于 2022-8-19 14:10:05 | 显示全部楼层 |阅读模式

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[Analog Circuits and Signal Processing] Pietro Buccella, Camillo Stefanucci, Mah.pdf (7.87 MB, 下载次数: 70 )
978-3-319-74382-0.jpg
Title: Parasitic Substrate Coupling in High Voltage Integrated Circuits Edition: 1st ed.
Author(s): Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
Publisher: Springer
Year: 2018
Pages: XVII, 183
DOI owner: Springer-Verlag
Language:English
Crossref Book ID:B3009528
Tags:Circuits and Systems; Electronic Circuits and Devices; Electronics and Microelectronics, Instrumentation; Engineering
book

Edition ID: 138027615
Added: 2018-08-15 07:07:45
Modified: 2022-04-09 09:40:24








This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.
The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.
The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.
Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
[...]


Front Matter ....Pages i-xvii
Overview of Parasitic Substrate Coupling (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 1-9
Design Challenges in High-Voltage ICs (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 11-39
Substrate Modeling with Parasitic Transistors (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 41-68
TCAD Validation of the Model (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 69-96
Extraction Tool for the Substrate Network (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 97-112
Parasitic Bipolar Transistors in Benchmark Structures (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 113-143
Substrate Coupling Analysis and Evaluation of Protection Strategies (Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese)....Pages 145-174 [...]



发表于 2022-8-19 21:39:06 | 显示全部楼层
kanakna
发表于 2022-8-20 13:23:10 | 显示全部楼层
下载看看
发表于 2022-8-20 20:30:19 | 显示全部楼层
谢谢分享
发表于 2023-10-8 18:19:07 | 显示全部楼层
谢谢分享这么好的资料
发表于 2023-10-18 09:27:25 | 显示全部楼层
针对高压集成电路的衬底耦合效应,非常不错
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