求助IC5141 DRC error

dinghao321

各位大侠，我用的0.13um工艺，在做calibre DRC的时候出现下面两个error，请教一下该如何修改，谢谢！

1、The BORDER layer must enclose all chip layout patterns, which all chip layout patterns include seal ring if seal ring has been added by designers.

This rule checking includes the layers of DNW,AA,NW,NC,PC,MVN, MVP,DG,GT,SN,SP,SAB,CT,M1,V1,Mn,Vn,P2,TMn,TVn,PA,MD,Fuse,ALPA,AADUM, GTDUM, MnDUM, TMnDUM.

2、Layout pattern (all chip design) minimum enclosure by chip edge (BORDER layer) is 0.73

fengrlove

SMIC要画BORDER layer。

dinghao321

fengrlove 发表于 2022-8-3 10:23
SMIC要画BORDER layer。

谢谢大佬

xiaoyunbaixue

模块级别的这个drc 错直接忽略。

inkel

选中图片中金属，摁“r”键，画一个框，将所画版图的内容框住。

铁肺孙大爷

fengrlove 发表于 2022-8-3 10:23
SMIC要画BORDER layer。

牛！