各位大侠,我用的0.13um工艺,在做calibre DRC的时候出现下面两个error,请教一下该如何修改,谢谢!
1、The BORDER layer must enclose all chip layout patterns, which all chip layout patterns include seal ring if seal ring has been added by designers. This rule checking includes the layers of DNW,AA,NW,NC,PC,MVN, MVP,DG,GT,SN,SP,SAB,CT,M1,V1,Mn,Vn,P2,TMn,TVn,PA,MD,Fuse,ALPA,AADUM, GTDUM, MnDUM, TMnDUM.
2、Layout pattern (all chip design) minimum enclosure by chip edge (BORDER layer) is 0.73
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