ARC HS4xFS Databook

eda2022

Introduction to the DesignWare ARC HS4xFS Processor Family
The ARC HS4xFSprocessor series implements the ARCv2™ instruction-set architecture in a
performance-optimized multi-stage pipeline. The ARCv2 instruction-set architecture is the next-generation
ISA for the DesignWare ARC family of configurable CPU/DSP cores.
The ARC HS4xFS processor can be configured as a single-core processor or a multi-core processor cluster
with optional inter-core communication and coherency components supporting symmetric as well as
asymmetric multi-processing programming models. An optional L2 Cache components can be added for
very high performance multi-core configurations.
Latest additions to the processor core include a high-performance dual-issue implementation which can
execute two instructions per cycle and DSP extensions for light applications. The DSP extensions include
arithmetic (add/sub, mul/madd, fixed point division and sqrt and butterfly ) operations, pointer address
calculations and format conversions (pack/unpack).
The processor family is complemented by the DesignWare Embedded Vision processor family utilizing a
very high-throughput vector unit and Convolutional Neural Network (CNN) cores. For more details, see
DesignWare EV6x Processor Databook and Programmer's Reference Manual for DesignWare EV6x Processors .





Architecture Highlights
The DesignWare ARC HS4xFS has numerous advanced features based on the ARCv2 instruction-set
architecture (ISA).
■ Instructions
❑ High-speed multiply, MAC and vector-arithmetic (SIMD) options
❑ Radix-4 divide option (int or fixed point )
❑ Fixed point square root option
❑ DSP extensions option
❑ Single-precision and double-precision floating-point options
❑ APEX facility to add custom instructions and interfaces for specialized applications
❑ User and kernel modes
❑ Efficient instruction encoding allows mixing 16- and 32 -bit instructions
❑Indexed instructions to save code space
❑ Support for 64-bit operands for selected basecase and custom instructions
■ Registers
❑ Configurable number of general-purpose core registers (16 or 32)
❑ Optional general-purpose register banks (up to eight register banks)
❑ Core registers may be paired for 64-bit support
❑ Special-purpose auxiliary-register space
❑ External auxiliary interface extension (UAUX) to connect third-party IP
❑ User may add custom core or auxiliary registers using APEX facility
❑ User may add custom core registers for address calculations (by the optional AGU)
Memory-addressing modes
❑ PC-relative addressing
❑ Address register pre- and post-index operations
❑ Stack-pointer support with multiple push/pop and range checking
❑ Scaled data-size addressing mode
❑ Non-aligned data addressing to save space
❑ Support for 64-bit load/store
❑ Memory-protection unit with programmable region size
❑ Up to 40 bits of addressing through optional memory-management unit
❑ Volatile (non-cacheable) region
❑ Optional peripheral region with a dedicated interface
❑ Memory-management unit supports internal CCMs
❑ Auto-advance pointer registers option with programmable step
Program flow
❑ Advanced branch-prediction hardware in base configuration
❑ Jumps and branches with optional delay slot
❑ Indexed branches
❑ Conditional ALU instructions
❑ Combined compare-and-branch instructions
❑ Zero-overhead loops
Interrupts and exceptions
❑ Maskable pulse- or level-triggered external interrupts, configurable from 0 to 240
❑ Up to 16 individually programmable priority levels
❑ Support for non-maskable exceptions, precise exceptions and memory-privilege exceptions
❑ Automatic save and restore of selected core registers upon entry and exit
❑ Optional core register banks can be used for fast context switching when servicing interrupts
❑ Exception-return instruction
❑ Interrupt and exception address-only vectors to save code space in smaller applications
Advanced instructions
❑ DSP and SIMD (vector arithmetic) with one-instruction-per-cycle throughput
❑ Bit manipulation and normalization
❑ Byte-level shifts, rotates, and endian reordering
❑ Byte and half-word shifts and rotations
❑ Enhanced radix-4 integer division option with a non-blocking graduation protocol





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