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发表于 2022-7-21 20:55:51
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Senior Digital Design Engineer 资深数字设计工程师
上海-闵行区
职位信息
1. Job Description
0. Develop RTL for digital IPs or systems based on architectural requirement, especially low power design implementation in IOT
1. Build testbench, create tests to verify design
2. Run check flow of lint, CDC analysis, top level integration, synthesis, timing/power analysis, timing closure, DFT-related task
2. Qualification
0. 5+ years of work experience in RTL design and Verification
1. Master’s degree in Microelectronics, Electronics, Electrical Engineer, Computer Science of relevant disciplines
2. Mandatory Tool Exposure: NCSim/VCS, DC,PT,Formality/LEC
3. Mandatory Skills: Verilog
4. Automation Tools: shell TCL Python etc.
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