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The Principles of Verifiable RTL Design Second Edition expands the discussion of assertion specification by including a new chapter entitled `Coverage, Events and Assertions'. All assertions exampled are aligned with the Open Verification Library Initiative proposed standard. Furthermore, the second edition provides expanded discussions on the following topics: - start-up verification;
- the place for 4-state simulation;
- race conditions;
- RTL-style-synthesizable RTL (unambiguous mapping to gates);
- more `bad stuff'.
The goal of the second edition is to keep the topic current. Principles of Verifiable RTL Design, Second Edition tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
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发表于 2008-1-5 15:25:28
