Increasesing the device Width (for a fixed current) will decrease the Vdsat of the PMOS device thats why you get lower Vdrop, for the 2nd question Vdo= Vout -Vin , so it makes perfect sence if Vin goes up Vdo goes down
in Figure C for the same current reducing the Vsg will require higher value for Vsd remeber the square law model (Ids=0.5*Un*Cox*W/L * (Vgs-vth)^2 .(1+lamda Vds) )