一些关于ＬＤＯ补偿的资料

XD0909

１．A NOVEL FREQUENCY COMPENSATION TECHNIQUE
FOR LOW-VOLTAGE LOW-DROPOUT REGULATOR

ABSTRACT
A novel frequency compensation technique for low-voltage
low-dropout regulator (LDR) is presented. The proposed technique,
called pole-control frequency compensation (PCFC), provides
faster loop response and does not require a large filtering
capacitor. Both theoretical analysis and simulation show that the
stability of the LDR using PCFC is independent of the load current,
temperature and equivalent series resistance of the filtering
capacitor. It is well suited for LDRs inside portable equipment
such as cellular phones, pagers and personal digital assistance.

XD0909

2.A Transient-Enhanced Low-Quiescent
Current Low-Dropout Regulator With
Buffer Impedance Attenuation

Abstract—This paper presents a low-dropout regulator (LDO)
for portable applications with an impedance-attenuated buffer for
driving the pass device. Dynamically-biased shunt feedback is proposed
in the buffer to lower its output resistance such that the
pole at the gate of the pass device is pushed to high frequencies
without dissipating large quiescent current. By employing the current-
buffer compensation, only a single pole is realized within the
regulation loop unity-gain bandwidth and over 65 phase margin
is achieved under the full range of the load current in the LDO. The
LDO thus achieves stability without using any low-frequency zero.
The maximum output-voltage variation can be minimized during
load transients even if a small output capacitor is used.
The LDO with the proposed impedance-attenuated buffer has
been implemented in a 0.35- m twin-well CMOS process. The
proposed LDO dissipates 20- A quiescent current at no-load
condition and is able to deliver up to 200-mA load current. With
a 1- F output capacitor, the maximum transient output-voltage
variation is within 3% of the output voltage with load step changes
of 200 mA/100 ns.

XD0909

3. Design of Low-Voltage Low-Dropout Regulator with
Wide-Band High-PSR Characteristic

Abstract—Utilizing a novel unit-gain compensation cell
(UGCC) to perform frequency compensation and power
supply rejection (PSR) enhancement, a low-voltage high-
PSR low-dropout regulator(LDO) is presented in this paper.
The proposed UGCC, consisting of a 1pF on-chip capacitor
and six transistors, effectively overcomes the drawbacks
that exist in the conventional compensation schemes by
generating an internal low-frequency zero. A LDO that
adopts this new structure is implemented and simulated
using a standard 0.18-μm CMOS process. Simulation
results show that the circuit can work properly when the
supply voltage is as low as 1.2V. The PSR over the
frequency range of dc to 1GHz is better than -40dB in all
cases at 1.2V supply voltage. The dropout voltage is 200mV
when the load current is 100mA. Therefore, it is well suited
for low-voltage ripple-sensitive applications.

lhtlht888

good, download to try!

xwj623

w123456

very good

crystalc

luoyih

thanks

guanjianl

Thanks a lot!