友友们，innovus后端求助啊！！！

497514980

1、**WARNIMPTS-403):   Delay calculation wasforced to extrapolate table data outside of the characterized range. In somecases, extrapolation can reduce the accuracy of the delay calculation. You canenable more detailed reporting of these cases by enabling the command 'setDelayCalMode-reportOutBound true'. Type 'man IMPTS-403' for more detail.

2、**WARNIMPCCOPT-1026): Did not meet theinsertion delay target of 1.600ns (+/- 0.054ns) for skew group ParClk/sdc.Achieved shortest insertion delay of 0.800ns.

Type 'man IMPCCOPT-1026' for more detail.

3、**WARNIMPCCOPT-1157): Did not meet themax_fanout constraint. Node the root driver for clock_tree ParClk at (-40.000,-12.200),in power domain auto-default, has 125 fanout.

4、**WARN:(IMPEXT-3530):      The process node isnot set. Use the command setDesignMode -process <process node> prior toextraction for maximum accuracy and optimal automatic threshold setting. Type'man IMPEXT-3530' for more detail.

5、**WARN:(IMPCCOPT-1059): Slackened off mininsertion delay target for skew_group ParClk/sdc from 1.545ns to 0.800ns.

**WARN: (IMPCCOPT-1059):      Slackened off min insertion delay targetfor skew_group SerClk/sdc from 0.146ns to 0.100ns.

6、#WARNING (NRGR-8)Clock net ParClk bottom preferred routing layer has been automatically set to 3for avoiding blocking other pins' access. If you don't want this setting,please set net ParClk bottom preferred routing layer as 1.

7、#WARNING(NRDB-2077) The below via enclosure for LAYER M1 is not specified for width0.090.

9、

**WARN: (IMPCCOPT-1076):      Leaf slew time target of 0.150ns is toolow. It needs to be increased to at least 0.189ns.

**WARN: (IMPCCOPT-1076):      Trunk slew time target of 0.150ns is toolow. It needs to be increased to at least 0.189ns.

**WARN: (IMPCCOPT-1076):      Top slew time target of 0.150ns is toolow. It needs to be increased to at least 0.189ns.

10.、**WARN:(IMPCCOPT-1184):     The library has nousable balanced inverters for power context:power_domain auto-default andeffective power_domain auto-default, while balancing clock_tree SerClk. If thisis not intended behavior, you can specify a list of lib_cells to use with theinverter_cells property.

大佬们，想问一下上面的warning怎么解决？ 我的sdc文件加载的是DC生成的sdc文件，centos中没法打开这个文件，需要安装什么编辑器才能打开这种类型的文件吗？

它一直报warning说我没指定工艺库，默认是是90nm，实际是65nm是怎么回事？整个后端流程我是通过点菜单进行的。在做CTS之前，一直要指定buffer类型吗，不指定buffer名字它会默认去库里找吗？

运行命令ccopt_design之后，Clock Tree Debugger中没有生成时钟树，啥也没有，报上面的那些warning。（本文设计只有两个异步时钟，寄存器级数很少）

Jashy

vim 就可以打开啊

497514980

   

Jashy 发表于 2021-12-31 14:51
vim 就可以打开啊

噢噢，谢啦老哥！

Jashy

1/2 你可以参考后面tool提示的man，自己去man一下那个tag
3，就是max fanout的问题，实际的fanout 大于你设置的值了，解fanout就不报了
4，setDesignMode -process 28/14/7  根据你的工艺，加一个这个命令就行
6，这个就是你的ParClk这条net的最低绕线层之前设置的是M1，tool自动改成M3了，因为M1 是出pin的layer，作为绕线层的话会有很多short和drc

别的还没仔细看