DC综合的时候

IC未入门的小波

Warning: In design 'top_interface5', the same net is connected to more than one pin on submodule 'mode5'. (LINT-33)
   Net 'w_reg_04[3]' is connected to pins 'error', 'reg_04[3]'.
Warning: In design 'osc_delay5', cell 'C83' does not drive any nets. (LINT-1)
Warning: In design 'error5', cell 'C364' does not drive any nets. (LINT-1)
Warning: In design 'error5', cell 'C375' does not drive any nets. (LINT-1)

Warning: In design 'ee_control5', cell 'C1595' does not drive any nets. (LINT-1)
Warning: In design 'ee_control5', cell 'C1651' does not drive any nets. (LINT-1)
Warning: In design 'abz5', cell 'B_127' does not drive any nets. (LINT-1)
Warning: In design 'abz5', cell 'B_128' does not drive any nets. (LINT-1)
Warning: In design 'abz5', cell 'C8047' does not drive any nets. (LINT-1)
Warning: In design 'abz5', cell 'C8059' does not drive any nets. (LINT-1)
Warning: In design 'abz5', cell 'C8089' does not drive any nets. (LINT-1)
Warning: In design 'abz5', cell 'C8098' does not drive any nets. (LINT-1)
Warning: In design 'abz5', cell 'B_133' does not drive any nets. (LINT-1)
Warning: In design 'abz5', cell 'B_134' does not drive any nets. (LINT-1)
#-----------------------------------------------------------------
# Save Pre-compiler Design
#-----------------------------------------------------------------
echo "+++++++++ Saving Pre-compiler Designn ..."
+++++++++ Saving Pre-compiler Designn ...
write -f ddc -hier -output ../out/${TOP_LEVEL}_pre.ddc
Writing ddc file '../out/top_interface5_pre.ddc'.
1
write -f verilog -hier -output ../out/${TOP_LEVEL}_pre.v
Writing verilog file '/home/leo/projects/TMR249_digit/control/dc/dc_all_bc_wc/read/out/top_interface5_pre.v'.
Warning: Module osc_delay5 contains unmapped components.  The output netlist might not be read back into the system. (VO-12)
Warning: Module error5 contains unmapped components.  The output netlist might not be read back into the system. (VO-12)
Warning: Module releas5 contains unmapped components.  The output netlist might not be read back into the system. (VO-12)
Warning: Module spi_control5 contains unmapped components.  The output netlist might not be read back into the system. (VO-12)
Warning: Module rst5 contains unmapped components.  The output netlist might not be read back into the system. (VO-12)
Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)
Warning: Module ee_control5 contains unmapped components.  The output netlist might not be read back into the system. (VO-12)
Warning: Module regist5 contains unmapped components.  The output netlist might not be read back into the system. (VO-12)
Warning: Verilog writer has added 90 nets to module abz5 using SYNOPSYS_UNCONNECTED_ as prefix.  Please use the change_names command to make the correct changes before invoking the verilog writer.  (VO-11)
Warning: Module abz5 contains unmapped components.  The output netlist might not be read back into the system. (VO-12)


请问遇到这种warning该如何debug，我只在一个简单模块的map 网表中查了一下，但是没理解悬空的原因
RTL如下，
module osc_delay5 (
                  input        sys_clk            ,
                  input        rst_n              ,
                  input        sclk               ,

                  output       osc                ,
                  output       osc_n              ,
                  output       nsclk
                  );

    reg   [9:0]    cnt_delay;
    reg            clk_n;
    wire           buf_osc;

always @  (posedge sys_clk or negedge rst_n) begin  // div  2
    if(rst_n==1'b0)
       clk_n <= 1'b0;
    else
       clk_n <= ~clk_n;
end

always @  (posedge  clk_n  or negedge  rst_n) begin  ///    osc delay
   if(rst_n==1'b0)
      cnt_delay <= 10'd0;
   else if (cnt_delay[9]==1'b0)
      cnt_delay <= cnt_delay+1'b1;
end

buffd20   buf5 (.Y(osc), .A(buf_osc));
assign  buf_osc = cnt_delay[9] ==1'b1 ? clk_n : 1'b1;
assign  osc_n= ~buf_osc;
assign  nsclk = ~sclk;
endmodule

serena.yao

请问博主这个问题解决了吗？我也遇到这个问题，不知道怎么解，求指导，谢谢。