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错误如下所示，子模块LVS均无错误，放在比较器版图里之后就报错了。
Error: Different numbers of instances (see below).
LAYOUT CELL NAME: pcmp2
SOURCE CELL NAME: pcmp2
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 7 7
Nets: 24 22 *
Instances: 45 17 * MN (4 pins)
56 19 * MP (4 pins)
6 0 * D (2 pins)
------ ------
Total Inst: 107 36
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 7 7
Nets: 13 13
Instances: 2 2 MN (4 pins)
6 6 MP (4 pins)
1 1 SMP2 (4 pins)
1 3 * _invv (4 pins)
0 2 * _invx4v (4 pins)
2 0 * _invx5v (4 pins)
2 2 _smn2v (4 pins)
------ ------
Total Inst: 14 16
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 (_invx5v) ** missing injected instance **
Devices:
X4/M1(10.725,-45.215) MP(P18)
X4/M0(10.415,-48.195) MN(N18)
X41/M16(12.785,-56.540) MP(P18)
X41/M1(15.365,-56.540) MN(N18)
X41/M17(12.785,-58.060) MP(P18)
X41/M2(15.365,-58.140) MN(N18)
X41/M19(12.785,-60.320) MP(P18)
X41/M4(15.365,-60.560) MN(N18)
X41/M23(12.785,-64.060) MP(P18)
X41/M8(15.365,-64.620) MN(N18)
--------------------------------------------------------------------------------------------------------------
2 (_invx5v) ** missing injected instance **
Devices:
X6/M1(24.725,-45.410) MP(P18)
X6/M0(25.035,-48.390) MN(N18)
X42/M16(22.785,-56.540) MP(P18)
X42/M1(20.205,-56.540) MN(N18)
X42/M17(22.785,-58.060) MP(P18)
X42/M2(20.205,-58.140) MN(N18)
X42/M19(22.785,-60.320) MP(P18)
X42/M4(20.205,-60.560) MN(N18)
X42/M23(22.785,-64.060) MP(P18)
X42/M8(20.205,-64.620) MN(N18)
--------------------------------------------------------------------------------------------------------------
3 ** missing injected instance ** (_invv)
Devices:
XI51/MPM0 MP(P18)
XI51/MNM0 MN(N18)
--------------------------------------------------------------------------------------------------------------
4 ** missing injected instance ** (_invv)
Devices:
XI50/MPM0 MP(P18)
XI50/MNM0 MN(N18)
--------------------------------------------------------------------------------------------------------------
5 ** missing injected instance ** (_invx4v)
Devices:
XI58/MPM0 MP(P18)
XI58/MNM0 MN(N18)
XI58/MPM2 MP(P18)
XI58/MNM2 MN(N18)
XI58/MPM3 MP(P18)
XI58/MNM3 MN(N18)
XI58/MPM4 MP(P18)
XI58/MNM4 MN(N18)
--------------------------------------------------------------------------------------------------------------
6 ** missing injected instance ** (_invx4v)
Devices:
XI57/MPM0 MP(P18)
XI57/MNM0 MN(N18)
XI57/MPM2 MP(P18)
XI57/MNM2 MN(N18)
XI57/MPM3 MP(P18)
XI57/MNM3 MN(N18)
XI57/MPM4 MP(P18)
XI57/MNM4 MN(N18)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 7 7 0 0
Nets: 13 13 0 0
Instances: 2 2 0 0 MN(N18)
6 6 0 0 MP(P18)
1 1 0 0 SMP2
1 1 0 2 _invv
0 0 0 2 _invx4v
0 0 2 0 _invx5v
2 2 0 0 _smn2v
------- ------- --------- ---------
Total Inst: 12 12 2 4
o Statistics:
6 layout instances were filtered and their pins removed from adjoining nets.
84 layout mos transistors were reduced to 21.
63 mos transistors were deleted by parallel reduction.
2 unused layout mos transistors were deleted.
o Initial Correspondence Points:
Ports: AVDD AVSS VIP CLKC VIN VON VOP
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发表于 2021-10-25 21:08:11
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