全定制设计交流

chip_idea · 发表于 2021-8-17 10:05:14

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刚刚毕业, 有一个工作机会, 从事NPU方向的全定制设计,需要定制逻辑电路及标准单元优化.
请问大神这个方向怎么样? 有没有大神做过定制化的电路和优化. 国内哪家公司技术能力最强?

谢谢!

秦时明月sw · 发表于 2021-8-17 16:17:57

哪家公司呀？

runforbetter · 发表于 2021-8-17 17:19:57

ai 和虚拟货币的思路有点类似，目前stdcell 定制，国内做的比较早的是海思，另外就是虚拟货币的几家公司了

aixingril · 发表于 2021-9-1 15:55:54

" Vim with all enhancements
source $VIMRUNTIME/vimrc_example.vim
" Use the internal diff if available.
" Otherwise use the special 'diffexpr' for Windows.
if &diffopt !~# 'internal'
set diffexpr=MyDiff()
endif
function MyDiff()
let opt = '-a --binary '
if &diffopt =~ 'icase' | let opt = opt . '-i ' | endif
if &diffopt =~ 'iwhite' | let opt = opt . '-b ' | endif
let arg1 = v:fname_in
if arg1 =~ ' ' | let arg1 = '"' . arg1 . '"' | endif
let arg1 = substitute(arg1, '!', '\!', 'g')
let arg2 = v:fname_new
if arg2 =~ ' ' | let arg2 = '"' . arg2 . '"' | endif
let arg2 = substitute(arg2, '!', '\!', 'g')
let arg3 = v:fname_out
if arg3 =~ ' ' | let arg3 = '"' . arg3 . '"' | endif
let arg3 = substitute(arg3, '!', '\!', 'g')
if $VIMRUNTIME =~ ' '
if &sh =~ '\<cmd'
if empty(&shellxquote)
let l:shxq_sav = ''
set shellxquote&
endif
let cmd = '"' . $VIMRUNTIME . '\diff"'
else
let cmd = substitute($VIMRUNTIME, ' ', '" ', '') . '\diff"'
endif
else
let cmd = $VIMRUNTIME . '\diff'
endif
let cmd = substitute(cmd, '!', '\!', 'g')
silent execute '!' . cmd . ' ' . opt . arg1 . ' ' . arg2 . ' > ' . arg3
if exists('l:shxq_sav')
let &shellxquote=l:shxq_sav
endif
endfunction
exec 'cd ' . fnameescape('D:\MyCode')
" gVim Setup
"set smarttab " 根据文件中其他地方的缩进空格个数来确定一个 tab 是多少个空格
set tabstop=4 " 表示一个 tab 显示出来是多少个空格
set shiftwidth=4 " 每一级缩进是多少个空格
set expandtab " 将tab扩展成空格
set number " 打开行号
set guifont=Consolas:h12
colorscheme desert " 色彩方案
set lines=40 columns=120 "启动时窗口大小
:set backspace=indent,eol,start
:set paste
" :map ?--定制映射
" :ab --定制简写
"===============================================================
" Add File Header
"===============================================================
:map <F1> :call AddHeader()<CR>
function AddHeader()
call append(0, "//=======================================================================")
call append(1, "// Company : ")
call append(2, "// Filename : .v")
call append(3, "// Author : Rongye")
call append(4, "// Created On : ".strftime("%Y-%m-%d %H:%M"))
call append(5, "// Last Modified : ")
call append(6, "// Description : ")
call append(7, "// ")
call append(8, "// ")
call append(9, "//=======================================================================")
endfunction<Enter>
"对齐注释
:map duiqi3 0f/i <ESC>073ldw
"===============================================================
" Add Modify Time
"===============================================================
:map <F2> :w<CR>:6d<CR>:call AddModify()<CR>
function AddModify()
call append(5, "// Last Modified : ".strftime("%Y-%m-%d %H:%M"))
endfunction
"===============================================================
" Add Module
"===============================================================
:ab modu module MODULE_NAME<Enter>#(<Enter> <ESC>04ldwi parameter <ESC>048ldwi WIDTH <ESC>060ldwi = 8 <ESC>072ldwi //<Enter><Esc>4Xi)<Enter>(<Enter> <ESC>04ldwi //Input<Enter> <ESC>04ldwi input <ESC>048ldwi clk <ESC>072ldwi ,<Enter> <ESC>04ldwi input <ESC>048ldwi rst_n <ESC>072ldwi ,<Enter> <ESC>04ldwi input <ESC>048ldwi en <ESC>072ldwi ,<Enter> <ESC>04ldwi input <ESC>024ldwi [WIDTH-1:0] <ESC>048ldwi data_i <ESC>072ldwi , //<Enter> <ESC>04ldwi //Output<Enter> <ESC>04ldwi output <ESC>016ldwi reg <ESC>024ldwi [WIDTH-1:0] <ESC>048ldwi data_o <ESC>072ldwi //<Enter>);<Esc>^4X$i<Enter><Enter><Enter><Enter>endmodule<Esc>kkk
"===============================================================
" Add input/output
"===============================================================
:ab inpu1 input <Esc>024ldwi [NAME_WIDTH-1:0] <Esc>048ldwi input_name <Esc>072ldwi , //
:ab outp1 output <ESC>016ldwi reg <Esc>024ldwi [NAME_WIDTH-1:0] <Esc>048ldwi output_name <Esc>072ldwi , //
"===============================================================
" Add reg
"===============================================================
:ab reg1 reg <Esc>048ldwi reg_name <Esc>072ldwi ; //
:ab reg2 reg <Esc>024ldwi [NAME_WIDTH-1:0] <Esc>048ldwi reg_name <Esc>072ldwi ; //
"===============================================================
" Add wire
"===============================================================
:ab wire1 wire <Esc>048ldwi wire_name <Esc>072ldwi ; //
:ab wire2 wire <Esc>024ldwi [NAME_WIDTH-1:0] <Esc>048ldwi wire_name <Esc>072ldwi ; //
"===============================================================
" Add parameter
"===============================================================
:ab para1 parameter <ESC>048ldwi NAME_WIDTH <ESC>060ldwi = 8 <ESC>072ldwi , //
"===============================================================
" Add always statement
"===============================================================
:ab zuhe always @(*)begin<Enter><Enter><Enter>end<Esc>kk
:ab shixu always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter><Enter>end<Enter>else begin<Enter><Enter>end<Enter><Esc>4Xiend<Esc>kk
"===============================================================
" Add if / else statement
"===============================================================
:ab if1 if(!rst_n)begin<Enter><Enter>end<Esc>kk
:ab else1 else begin<Enter><Enter>end<Esc>kk
"===============================================================
" Add case statement
"===============================================================
:ab case1 case()begin<Enter>1'b0:;<Enter>1'b1:;<Enter>default:;<Enter><Esc>4Xiendcase<Esc>kk
"===============================================================
" Add Counter
"===============================================================
:ab jishu reg <Esc>024ldwi [NAME_WIDTH-1:0] <Esc>048ldwi cnt <Esc>072ldwi ; //<Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>cnt <= 4'd0;<Enter>end<Enter>else if(cnt==4'd9)begin<Enter>cnt <= 4'd0;<Enter>end<Enter>else begin<Enter>cnt <= cnt + 1'd1;<Enter>end<Enter>end<Enter><Esc>
"===============================================================
" Add FSM_2
"===============================================================
:ab fsm2 reg <Esc>024ldwi [NAME_WIDTH-1:0] <Esc>048ldwi state_current <Esc>072ldwi ; //<Enter>reg <Esc>024ldwi [NAME_WIDTH-1:0] <Esc>048ldwi state_next<Enter>reg <Esc>048ldwi FSM_out <Esc>072ldwi ; //<Enter><Enter>always @(posedge clk or negedge rst_n)begin<Enter>if(!rst_n)begin<Enter>state_current <= IDLE;<Enter>end<Enter>else begin<Enter>state_current <= state_next;<Enter>end<Enter>end<Enter><Enter><Enter>always @(*)begin<Enter>FSM_out = 1'b0;<Enter>case(state_current)<Enter>IDLE:begin<Enter>if(FSM_in)<Enter>state_next = S1;<Enter>else<Enter>state_next = state_current;<Enter>end<Enter>S1:begin<Enter>if(FSM_in)<Enter>state_next = S2;<Enter>else<Enter>state_next = state_current;<Enter>end<Enter>S2:begin<Enter>if(FSM_in)begin<Enter>FSM_out = 1'b1;<Enter>state_next = IDLE;<Enter>end<Enter>else<Enter>state_next = state_current;<Enter>end<Enter><Enter>default:state_next = IDLE;<Enter>endcase<Enter>end<Enter>

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[原创] 全定制设计交流

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