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发表于 2007-12-11 09:13:54
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Abstract
Nowadays, it is possible to integrate millions of transistors in a single chip by using
submicron CMOS processes. Simultaneously, the speed of digital circuits has increased up
to the gigahertz range. With the ongoing advance of the CMOS digital technology, the
trend is that digitizing an analog signal and performing digital signal processing is as early
as possible in a signal processing system, to eliminate the requirements of accurate and
expensive traditional analog building blocks. However, early signal digitization increases
requirements on the analog-to-digital converters (ADCs) regarding resolution and
bandwidth. Particularly in the modern communication systems, over 14-bit signal-to-noise
ratio and 90-dB spurious-free dynamic-range should be satisfied, in order to avoid that
small analog input signals are masked under the distortions by intermodulation products
with the interfering signals. The other simultaneously desired key performance of ADCs is
the conversion rate from tens of MSample/s to hundreds of MSample/s in the future
communication systems to meet the growing needs of the high-capacity and high-speed
data transfer.
As the desired signal conversion rate increases, integrator defective settling becomes the
main bottleneck in the present wideband Switch-Capacitor (SC) Sigma-Delta modulators.
In this thesis, a systematic approach for designing high-speed high-resolution Sigma-Delta
modulators is introduced. This approach has been adopted in designing a high-order
cascade multi-bit Sigma-Delta modulator in the 0.4 u SiGe-BiCMOS process, which was
donated by Freescale Semiconductor, Inc. Therefore, a power efficient implementation has
been obtained in a short design cycle. In this design, high-performance analog circuits,
such as opamp, bandgap, etc., have been designed in the SiGe-BiCMOS process. It shows
that by properly using the BiCMOS process, the conversion rate of the Sigma-Delta
modulator integrators can be greatly improved without the degradation of the achievable
resolution.
A substantial part of the work is to develop a simulation tool. With its assistance the nonideal
effects and corresponding improved structures can be well simulated in sigma delta
modulators. As alternatives, a novel low-disortion cascade and a low-disortion cascade
VI
multi-bit Sigma-Delta modulator with improved noise-transfer-function (NTF) have been
proposed in the mainstream CMOS process. Both architectures combine the merits of lowdistortion,
cascaded Sigma-Delta structure and multi-bit quantization to achieve high
dynamic range at low oversampling ratio of 8. A comprehensive analysis of both proposed
architectures in comparison with the traditional high-order Sigma-Delta modulator
architectures has been performed. It shows that both architectures are fundamentally
immue to the finite integrator settling and other circuit non-idealities, such as finite and
non-linear DC-gain of opamps, capacitor mismatching, etc. Additionally, the second one
exhibits an SNR improvement over 10 dB against theoretical value. These overall
outstanding advantages have been validated by behavior simulation. The proposed
architectures are potentially suitable for wideband and low-power applications with deep
sub-micron CMOS processes. |
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发表于 2007-12-11 09:12:58
