AMS仿真报错

shzhzhao · 发表于 2021-3-22 11:41:51

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AMS仿真报错但是信息提示里并没有error,请问这是什么错误，提示信息如下：
INFO (AMS-2142): The AMS Unified Netlisting (AMS UNL) flow has been enabled.
INFO (AMS-2031): The instances bound to the views specified in the 'Netlist using spectre CDF simInfo'
field in the Netlister form (Simulation->Options->Netlister) will be netlisted as
analog primitives using the Spectre CDF simulation information.
Begin Netlisting Mar 22 11:39:37 2021
WARNING (OSSHNL-143): Incremental netlisting is not possible since the global map file '/home/zzz/simulation/AandD/ams/config/netlist/digital/ihnl/globalmap', could
not be opened in the read mode for IHNL version number comparison. Therefore
re-netlisting the entire design.

INFO (VLOGNET-60): The stimulus name mapped table will not be printed in the
"/home/zzz/simulation/AandD/ams/config/netlist/digital/testfixture.verilog" file. To print the stimulus name mapped table, set
simVerilogPrintStimulusNameMappingTable = t either in CIW or the .simrc file
before invoking Verilog netlister.

INFO (VLOGNET-62): Database internal net names will be printed for floating instance ports. To prevent
them from being printed, set simVerilogProcessNullPorts = t either in CIW or
the .simrc file.

INFO (VLOGNET-64): All cellviews in the design will be printed in the Netlist Configuration list.
If you want to print only those cellviews that need to be re-netlisted in the
list, set simVerilogIncrementalNetlistConfigList = t either in CIW or the
.simrc file.

INFO (VLOGNET-68): The initial state of stimulus of all inout pins is set to "z". To get inout
pins with initial state of "0", set hnlVerilogIOInitStimulusStr = "0"
either in CIW or the .simrc file.

ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.
*ERROR* (AMS-1247): AMS UNL netlisting has failed.
Check Simulation->Output Log->Netlister Log for errors.
Correct your design and netlist again.
...unsuccessful.

fhy420462303 · 发表于 2021-3-23 13:54:25

按照提示
Check Simulation->Output Log->Netlister Log
你会发现有ERROR信息的！

zjguo · 发表于 2021-3-25 09:41:35

我和您一样情况，请问您解决了嘛

zjguo · 发表于 2021-3-25 10:58:58

Begin Netlisting Mar 25 10:52:52 2021
WARNING (OSSHNL-143): Incremental netlisting is not possible since the global
map file
'/home/meow/simulation/tb_test/ams/config/netlist/digital/ihnl/globalmap',
could
not be opened in the read mode for IHNL version number comparison.
Therefore
re-netlisting the entire design.

INFO (VLOGNET-60): The stimulus name mapped table will not be printed in the

"/home/meow/simulation/tb_test/ams/config/netlist/digital/testfixture.verilog"
file. To print the stimulus name mapped table, set

simVerilogPrintStimulusNameMappingTable = t either in CIW or the .simrc file

before invoking Verilog netlister.

INFO (VLOGNET-62): Database internal net names will be printed for floating
instance ports. To prevent
them from being printed, set
simVerilogProcessNullPorts = t either in CIW or
the .simrc file.

INFO (VLOGNET-64): All cellviews in the design will be printed in the Netlist
Configuration list.
If you want to print only those cellviews that need to be
re-netlisted in the
list, set simVerilogIncrementalNetlistConfigList = t either
in CIW or the
.simrc file.

INFO (VLOGNET-68): The initial state of stimulus of all inout pins is set to
"z". To get inout
pins with initial state of "0", set
hnlVerilogIOInitStimulusStr = "0"
either in CIW or the .simrc file.