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新鲜出炉的JSSC Volume-42 Issue-11
目录
A 19.7 MHz, Fifth-Order Active-RC Chebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 $mu{hbox {m}}$ CMOS Technology
Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS
A 2.5-V 14-bit, 180-mW Cascaded $SigmaDelta$ ADC for ADSL2+ Application
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL
A 16-Mb Toggle MRAM With Burst Modes
A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration
A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers
Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs
A 1.1 GHz Fifth Order Active-LC Butterworth Type Equalizing Filter
Nonlinear Shaping SC Oscillator With Enhanced Linearity
A 0.9 V 96 $mu$W Fully Operational Digital Hearing Aid Chip
A Monolithic Buck Converter With Near-Optimum Reference Tracking Response Using Adaptive-Output-Feedback
Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications
A Sub-1-V Low-Noise Bandgap Voltage Reference
Linear Current-Mode Active Pixel Sensor
Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 $Omega$ Signal-Source Impedance
A Low Reference Spurs 1–5 GHz 0.13 $mu$m CMOS Frequency Synthesizer Using a Fully-Sampled Feed-Forward Loop Filter
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication
A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells
0.13-$mu$m CMOS Phase Shifters for X-, Ku-, and K-Band Phased Arrays
[ 本帖最后由 skybridge 于 2007-12-10 10:30 编辑 ] |
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发表于 2007-12-6 12:52:40
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