求助，DC综合后 worst slack 负的特别多 -10000多不知所措该从何下手解决呢

Bricool · 发表于 2020-11-26 15:49:59

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本帖最后由 Bricool 于 2020-11-26 15:51 编辑

Information: Updating design information... (UID-85)
Warning: Design 'RSA' contains 13 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)

****************************************
Report : timing
      -path full
      -delay max
      -max_paths 1
Design : RSA
Version: P-2019.03-SP2
Date : Thu Nov 26 15:45:49 2020
****************************************

* Some/all delay information is back-annotated.

# A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: ss_v1p62_125c Library: scc018ug_hd_rvt_ss_v1p62_125c_basic
Wire Load Model Mode: Inactive.

  Startpoint: address[0] (input port clocked by clk)
  Endpoint: datap/KEYREG/q1_reg[198]
         (rising edge-triggered flip-flop clocked by clk)
  Path Group: INPUT
  Path Type: max

  Point                                  Incr    Path
  -----------------------------------------------------------
  clock clk (rise edge)                   0.00    0.00
  clock network delay (ideal)             1.00    1.00
  input external delay                   2.00    3.00 r
  address[0] (in)                         0.14    3.14 r
  U234/ZN (INHDV2)                      0.09 *    3.24 f
  U214/ZN (CLKNAND2HDV4)                0.12 *    3.36 r
  U4552/ZN (NOR2HDV16)                   0.08 *    3.44 f
  datap/U11287/ZN (NOR3BBHDV0)       11904.30 * #
                                                11907.74 r
  datap/U9282/ZN (INHDV2)             -426.59 # 11481.14 f
  datap/U9285/ZN (NAND2BHDV0)          174.63 * 11655.78 f
  datap/U9288/ZN (NOR2BHDV0)             3.41 * 11659.18 f
  datap/U27116/ZN (INHDV2)                0.41 * 11659.60 r
  datap/KEYREG/q1_reg[198]/D (DQHDV4)    0.00 * 11659.60 r
  data arrival time                            11659.60

  clock clk (rise edge)                10.00    10.00
  clock network delay (ideal)             1.00    11.00
  clock uncertainty                      -0.70    10.30
  datap/KEYREG/q1_reg[198]/CK (DQHDV4)    0.00    10.30 r
  library setup time                   -0.10    10.20
  data required time                               10.20
  -----------------------------------------------------------
  data required time                               10.20
  data arrival time                            -11659.60
  -----------------------------------------------------------
  slack (VIOLATED)                               -11649.40
-10000多被吓到不知从何处着手解决希望有大神指点