JSSC 2020_01_07 ADC合集

icisee

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112-Gb-s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels.pdf
A 1.6-GS-s 12.2-mW Seven--Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration.pdf
A 10-bit 120-MS-s SAR ADC With Reference Ripple Cancellation Technique.pdf
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC.pdf
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer.pdf
A 14-bit 4-MS-s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration.pdf
A 161-mW 56-Gb-s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.pdf
A 243-mW 1.25-56-Gb-s Continuous Range PAM-4 42.5-dB IL ADC-DAC-Based Transceiver in 7-nm FinFET.pdf
A 4-GS-s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs.pdf
A 5-GS-s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS.pdf
A 5-GS-s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ-cs.pdf
A Continuous-Time Zoom ADC for Low-Power Audio Applications.pdf
A Highly Linear OTA-Less 1-1 MASH VCO-Based  --Delta-Sigma-  ADC With an Efficient Phase Quantization Noise Extraction Technique.pdf
A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping.pdf
A Second-Order Purely VCO-Based CT  --Delta-Sigma-  ADC Using a Modified DPLL Structure in 40-nm CMOS.pdf
A Temperature-Stabilized Single-Channel 1-GS-s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier.pdf

xiaofuss111

感谢

jiaoda

正需要，真是懒人福利

小琛

感谢感谢！拿去学习了

落雪听禅

不错，收下了！

student321

kankan

newrfdesign

thanks

zheshiwo

谢谢分享！

cdting

Thanks!!!

中国

谢谢分享