外企北京深圳上海 Principal Verification Engineer

Emmayi · 发表于 2020-7-23 13:29:10

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外企_办公地址：北京深圳上海
简历发emma.yin@yaxunhr.com
WeChat：18938078656
Principal Verification Engineer
Position Requirements: 4-6 or above years’ experience in the following areas:

1. Design experience in Verilog/VHDL for IP or SoC chip level.
2. HW verification with knowledge of System Verilog/VHDL and HDL simulators
3. Experience with hardware emulator or accelerator is a big advantage
4. Advanced Verification Methodology like UVM is a plus
5. Knowledge of Unix and Linux is highly desired
6. Strong verbal and written communication skills in English
7. Strong teamwork skills with good human relationship