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XTALL

芯片验证工程师
地点：北京、上海；
职级：P7-P8不等；
工作年限：3年起，可适当放宽。

JD Description:
* Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
* Contribute significantly to verification infrastructure development
* Development of System Verilog/UVM based protocol/traffic generators/checkers, development of test plan based on functional requirements
Job Requirements:
Masters degree desired, Bachelor's degree in CS/EE is required. 5+ years of relevant experience in ASIC verification field.
* Should have worked on developing/implementing test plans at the chip-level for complex ASICs.
* Fluent in System Verilog and scripting languages such as Python or Perl.
* Must have intimate knowledge of UVM methodology.
* Experience in the verification of SoC and other IPs such as CPU Subsystem, Ethernet, PCIE, DDR, Serdes etc.
* Knowledgeable about assertions and functional coverage
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Very good communication skills and ability and desire to work in a geographically diverse team environment.
* Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs

联系方式：站内信 OR 邮件（wb-gf308674@alibaba-inc.com）